Xilinx Virtex-4 - Transmit Clocking Scheme

148 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 5: Miscellaneous Functions
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Transmit Clocking Scheme
Figure 5-1 shows the clocks used in the transmit module of the Ethernet MAC. In this
figure, TX_CORE_CLK and TX_GMII_MII_CLK are internal clock signals.
The clock generation module uses the PHYEMAC#GTXCLK (1 Gb/s) and
PHYEMAC#MIITXCLK (10/100 Mb/s) inputs to generate
EMAC#CLIENTTXCLIENTCLKOUT to run the circuitry in the FPGA fabric connecting to
the client side. The CLIENTEMAC#TXCLIENTCLKIN signal runs the client logic and
transmit engine inside the Ethernet MAC. This clock signal must be from the FPGA clock
drivers (BUFG) of EMAC#CLIENTTXCLIENTCLKOUT.
On the physical interface side, when the Ethernet MAC is configured in GMII, MII, or
RGMII mode, EMAC#CLIENTTXGMIIMIICLKOUT drives the clock in the FPGA fabric
connecting to the GMII/MII/RGMII sublayer. EMAC#CLIENTTXGMIIMIICLKOUT is
also fed back into CLIENTEMAC#TXGMIIMIICLKIN.
The CLIENTEMAC#TXGMIIMIICLKIN signal runs the MII/GMII/RGMII logic inside the
Ethernet MAC. This clock signal must be from the FPGA clock drivers (BUFG) of
EMAC#CLIENTTXGMIIMIICLKOUT. When Ethernet MAC is configured in SGMII or
1000BASE-X mode, TX_GMII_MII_CLK is driven by PHYEMAC#GTXCLK, and the
CLIENTEMAC#TXGMIIMIICLKIN clock is not used.
When configured in MII mode, EMAC#CLIENTTXGMIIMIICLKOUT is derived from
PHYEMAC#MIITXCLK. When configured in either GMII, RGMII, SGMII, or 1000BASE-X
Table 5-5: Host Interface and MDIO Clock Frequencies
Clock Signals Direction Frequency
HOSTCLK Input Up to 125 MHz.
DCREMACCLK Input The same clock frequency as the PowerPC clock, CPMC405CLOCK.
Must be phase-aligned with the PowerPC clock.
EMAC#PHYMCLKOUT Output Not to exceed 2.5 MHz for IEEE Std 802.3 compliance.
Figure 5-1: Transmit Clock
CLKGEN
TX
Core
TX
Client
Datapath
Synchronous
Buffer
GMII/MII
PCS/PMA
TX_CORE_CLK
TX_GMII_MII_CLK
EMAC#CLIENTTXCLIENTCLKOUT
EMAC#CLIENTTXGMIIMIICLKOUT
EMAC#PHYTXCLK
PHYEMAC#MIITXCLKPHYEMAC#GTXCLK
Ethernet MAC Block
CLIENTEMAC#TXGMIIMIICLKIN
CLIENTEMAC#TXCLIENTCLKIN
ug074_3_01_101904
Client
Logic
GMII/
MII/RGMII
Logic
BUFG BUFG
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