Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 97
UG074 (v2.2) February 22, 2010
MDIO Interface
R
Figure 3-51 illustrates a third user case example that does not use the host interface, but
instead uses an external STA (MDIO master). Figure 3-51 shows this as an external device
to the FPGA, but the EMAC’s Managements Data Input/Output (MDIO) Interface signals
can alternatively be connected directly to a STA implemented in the FPGA fabric.
.
This functionality is obtained by asserting High TIEEMAC#CONFIGVEC[73] (MDIO
enable) and pulling Low TIEEMAC#CONFIGVEC[67] (Host Interface enable) when not
using the host interface. In this case, the MDC clock must be provided through the input
port PHYEMAC#MCKIN.
Accessing MDIO via the EMAC Host Interface
The host interface can be used to provide STA (MDIO master) functionality. The remainder
of this chapter details how to access this functionality via the host interface.
The MDIO interface supplies a clock to the external devices, EMAC#PHYMCLKOUT
when the host interface is enabled. This clock is derived from the HOSTCLK signal using
the value in the Clock Divide[5:0] configuration register. The frequency of the MDIO clock
is given by the following equation:
To comply with the IEEE Std 802.3-2002 specification for this interface, the frequency of
EMAC#PHYMCLKOUT should not exceed 2.5 MHz. To prevent EMAC#PHYMCLKOUT
from being out of specification, the Clock Divide[5:0] value powers up at 000000. While
this value is in the register, it is impossible to enable the MDIO interface. Given this, even
if the user has enabled the host interface and the MDIO interface by tieing both
TIEEMAC#CONFIGVEC[67] and TIEEMAC#CONFIGVEC[73] High. Upon reset, the
MDIO port is still disabled until a non-zero value has been written into the clock divide
bits. When the host interface is disabled, the user can still access the management registers
in the internal PCS/PMA layer by providing PHYEMAC#MCLKIN and tying
TIEEMAC#CONFIGVEC[73] High.
Access to the MDIO interface through the management interface is shown in the
Figure 3-52 timing diagram.
Figure 3-51: User Case 3: External MDIO Access to the PCS/PMA Sublayer
Address Filter Registers
MDIO Interface
(STA MDIO Master)
Configuration Registers
PCS/PMA
Sublayer
(MMD
MDIO Slave)
EMAC#
EMAC#PHYMCLKOUT
PHYEMAC#MCLKIN
PHYEMAC#MDIN
EMAC#PHYMDOUT
EMAC#PHYMDTRI
NC
External STA
(MDIO Master)
Host
Interface
IBUF
IPAD
I
O
O
I
IO
T
IOPAD
IOBUF
MDC
MDIO
MDIO
Arbitration
UG074_3_76_112705
f
MDC
f
HOSTCLK
1 Clock Divide[5:0]+()2×
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English