EasyManua.ls Logo

Xilinx Virtex-4 - Page 96

Xilinx Virtex-4
176 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
96 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
R
Figure 3-50 illustrates a second implementation example. The host interface is used as the
MDIO master to access the configuration registers of the PCS/PMA sublayer logic, which
contains an MDIO slave. All connections are internal and are enabled by pulling
TIEEMAC#CONFIGVEC[73] (MDIO enable) High.
In this example, the EMAC’s Managements Data Input/Output (MDIO) Interface signals
are not used. The output signals are left unconnected, and the input signals are tied to a
logic level. PHYEMAC#MDIN must be tied High when not connected to an external PHY.
Alternatively, the EMAC’s Managements Data Input/Output (MDIO) can be connected to
a second MMD (for example, an external PHY device) by providing the connections
illustrated in Figure 3-49. Externally connected MMDs (MDIO slaves) must have different
non-zero physical addresses (PHYAD) from the non-zero address of the PCS/PMA
sublayer.
Figure 3-50: User Case 2: Internal MDIO Access to PCS/PMA Sublayer
Host
Interface
Address Filter Registers
MDIO Interface
(STA MDIO Master)
Configuration Registers
PCS/PMA
Sublayer
(MMD
MDIO Slave)
EMAC#
EMAC#PHYMCLKOUT
PHYEMAC#MCLKIN
PHYEMAC#MDIN
EMAC#PHYMDOUT
EMAC#PHYMDTRI
GND
NC
NC
NC
UG074_3_75_112705
VCC
MDIO
Arbitration
www.BDTIC.com/XILINX

Table of Contents

Other manuals for Xilinx Virtex-4

Related product manuals