26 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 2: Ethernet MAC Architecture
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Host Interface Signals
Host Bus Signals
Table 2-5 outlines the host bus interface signals.
Table 2-5: Host Bus Signals
Signal Direction Description
HOSTCLK Input
Clock supplied for running the host. User must supply this clock
at all times even if the host interface is not used.
HOSTOPCODE[1:0] Input
Defines operation to be performed over MDIO interface. Bit [1] is
also used in configuration register access. See “Configuration
Registers” in Chapter 3.
HOSTADDR[9:0] Input Address of register to be accessed.
HOSTWRDATA[31:0] Input Data bus to write to register.
HOSTRDDATA[31:0] Output Data bus to read from register.
HOSTMIIMSEL Input
When asserted, the MDIO interface is accessed. When
deasserted, the Ethernet MAC internal configuration registers
are accessed.
HOSTREQ Input Used to signal a transaction on the MDIO interface.
HOSTEMAC1SEL Input
This signal is asserted when EMAC1 is being accessed through
the host interface and deasserted when EMAC0 is being accessed
through the host interface. It is ignored when the host interface is
not used.
HOSTMIIMRDY Output
When High, the MDIO interface has completed any pending
transaction and is ready for a new transaction.
Notes:
1. All signals are synchronous to HOSTCLK and are active High.
2. When using the PowerPC 405 processor as a host processor and using the DCR bus for host access, the host bus signals are used to
read the optional FPGA fabric-based statistics registers. See “Interfacing to an FPGA Fabric-Based Statistics Block” in Chapter 6.
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