Xilinx Virtex-4 User Manual

104 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
MII Signals
An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into the media independent interface. Table 4-1 describes the MII interface signals.
Figure 4-5: TX Acknowledge Register
Clock Enable
ACK seen here
Ethernet MAC expects it to be held until here
EMAC#CLIENTTXACK
Registered
EMAC#CLIENTTXACK
Data (with registered ACK)
D1
D1
D2
D2
D3
EMAC#CLIENTTXGMIIMIICLKOUT
PHYEMAC#RXCLK
EMAC#PHYTXD
PHYEMAC#RXD
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#RXCLIENTCLKIN
UG074_3_70_010906
Table 4-1: MII Interface Signals
Signal Direction Description
MII_TXD[3:0]_# Output Transmits data to PHY
MII_TX_EN_# Output Transmits data enable to PHY
MII_TX_ER_# Output Transmits error signal to PHY
MII_TX_CLK_# Input Recovered transmit clock by PHY
MII_CRS_# Input Carrier sense control signal from PHY
MII_COL_# Input Collision detect control signal from PHY
MII_RX_CLK_# Input Recovered clock from data stream by PHY
MII_RXD[3:0]_# Input Receive data from PHY
MII_RX_DV_# Input Receive data valid control signal from PHY
MII_RX_ER_# Input Receive data error signal from PHY
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English