Xilinx Virtex-4 - PCSPMA Signals; Management Registers

140 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
derived from the transmitter PLL, reflects the reference clock and drives the other clock
inputs. It connects through a global buffer to PHYEMAC#GTXCLK and into TXUSRCLK2
and RXUSRCLK2. TXUSRCLK and RXUSRCLK are not used and are tied to ground.
Because no GMII logic is in the 1000BASE-X PCS/PMA mode of configuration, the
EMAC#CLIENTTXGMIIMIICLKOUT output port is not connected, and the input port
CLIENTEMAC#TXGMIIMIICLKIN is connected to ground.
The EMAC#CLIENTTXCLIENTCLKOUT output port must be connected to the DCM
CLKIN input. The CLKDV output of the DCM, with the CLKDV_DIVIDE attribute set to
two, is routed to a BUFG and is connected to the transmit client logic and to
PHYEMAC#MIITXCLK. The CLK0 output of the DCM is routed to a BUFG and is
connected to the input port CLIENTEMAC#TXCLIENTCLKIN. This arrangement reduces
the clock rate on the 16-bit client interface to half of the PHYEMAC#GTXCLK. The clocks
generated by this DCM can also be shared with the receive clocks
CLIENTEMAC#RXCLIENTCLKIN and PHYEMAC#RXCLK as shown in Figure 4-28.
TXLOCK and RXLOCK from the MGT and the locked signals from the client interface
DCM are ANDed together to generate a combined lock signal for
CLIENTEMAC#DCMLOCKED. The lock signal ensures the Ethernet MAC does not
operate until the MGT has achieved all the necessary locks.
The phase-matched clock divider (PMCD) feature of certain Virtex-4 devices can be used to
replace the client interface DCM.
PCS/PMA Signals
An Ethernet MAC wrapper has all the necessary pin connections to configure the primitive
into 1000BASE-X PCS/PMA. Table 4-6 also describes the 1000BASE-X PCS/PMA interface
signals.
Management Registers
The PCS in the 1000BASE-X PCS/PMA sublayer contains the full managed register block
defined in IEEE Std 802.3-2002, Clause 37. This utilizes 10 dedicated management registers,
accessed from the MDIO interface. Table 4-10 to Table 4-19 define these 10 registers.
Table 4-10: Control Register (Register 0)
Bit(s) Name Description Attributes Default Value
0.15 Reset
1 = PCS/PMA reset.
0 = Normal operation.
Read/Write
Self Clearing
TIEEMAC#CONFIGVEC[78]
0.14 Loopback
1 = Enable loopback mode.
0 = Disable loopback mode.
Read/Write TIEEMAC#CONFIGVEC[74]
0.13
Speed Selection
(LSB)
The Ethernet MAC always returns a 0
for this bit. Along with bit 0.6, speed
selection of 1000 Mb/s is identified.
Returns 00
0.12
Auto-
Negotiation
Enable
1 = Enable auto-negotiation process.
0 = Disable auto-negotiation process.
Read/Write TIEEMAC#CONFIGVEC[77]
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