Xilinx Virtex-4 - Page 146

146 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
15.12
1000BASE-T
Half Duplex
The Ethernet MAC always returns a 0
for this bit because 1000BASE-T half
duplex is not supported.
Returns 00
15:11:0 Reserved Always returns 0s. Returns 0s 000000000000
Table 4-18: Extended Status Register (Register 15) (Cont’d)
Bit(s) Name Description Attributes Default Value
Table 4-19: Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)
Bit(s) Name Description Attributes Default Value
16.15:2 Reserved Always returns 0s. Returns 0s 00000000000000
16.1 Interrupt Status
1 = Interrupt is asserted.
0 = Interrupt is not asserted.
If the interrupt is enabled, this bit is
asserted upon the completion of an
auto-negotiation cycle; it can only be
cleared by writing 0 to this bit.
If the interrupt is disabled, this bit is set
to 0.
The EMAC#CLIENTANINTERRUPT
port is wired to this bit.
Read/Write 0
16.0 Interrupt Enable
1 = Interrupt is enabled.
0 = Interrupt is disabled.
Read/Write 1
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