Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 171
UG074 (v2.2) February 22, 2010
Timing Diagram and Timing Parameter Tables
R
Timing Diagram and Timing Parameter Tables
The timing relationships described in this section are shown in Figure A-1.
Table A-1 through Table A-6 list the timing parameters as reported by the implementation
tools relative to the clocks given in Table A-1, page 149, along with the Ethernet MAC
signals that are synchronous to each clock.
• Table A-1, “CLIENTEMAC#RXCLIENTCLKIN Switching Characteristics,” on
page 171
• Table A-2, “CLIENTEMAC#TXCLIENTCLKIN Switching Characteristics,” on
page 172
• Table A-3, “HOSTCLK Switching Characteristics,” on page 172
• Table A-4, “PHYEMAC#GTXCLK Switching Characteristics,” on page 173
• Table A-5, “PHYEMAC#MIITXCLK Switching Characteristics,” on page 174
• Table A-6, “PHYEMAC#RXCLK Switching Characteristics,” on page 174
Figure A-1: Ethernet MAC Timing Relative to Clock Edge
Tabl e A - 1 : CLIENTEMAC#RXCLIENTCLKIN Switching Characteristics
Parameter Function Signal
Clock To Out:
Tmaccko_ERROR Data Output EMAC#CLIENTRXBADFRAME
Tmaccko_CLKOUT Data Output EMAC#CLIENTRXCLIENTCLKOUT
Tmaccko_RXD Data Output EMAC#CLIENTRXD
Tmaccko_VALID Data Output EMAC#CLIENTRXDVLD
Tmaccko_VALID Data Output EMAC#CLIENTRXDVLDMSW
Tmaccko_FRAME Data Output EMAC#CLIENTRXFRAMEDROP
Tmaccko_FRAME Data Output EMAC#CLIENTRXGOODFRAME
Clock
Control
Inputs
Outputs
Clock High
T
MACCK
T
MACCKC
T
MACCKO
ug074_apA_01_020910
1
2
Data
Inputs
T
MACDCK
T
MACCKD
Clock Low
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English