Xilinx Virtex-4 User Manual

174 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Appendix A: Ethernet MAC Timing Model
R
Tmacckd_SYNC Data Hold PHYEMAC#RXLOSSOFSYNC
Tmacdck_SYNC Data Setup PHYEMAC#RXLOSSOFSYNC
Tmacckd_NOTINT Data Hold PHYEMAC#RXNOTINTABLE
Tmacdck_NOTINT Data Setup PHYEMAC#RXNOTINTABLE
Tmacckd_DISP Data Hold PHYEMAC#RXRUNDISP
Tmacdck_DISP Data Setup PHYEMAC#RXRUNDISP
Tmacckd_DETECT Data Hold PHYEMAC#SIGNALDET
Tmacdck_DETECT Data Setup PHYEMAC#SIGNALDET
Tmacckd_ERROR Data Hold PHYEMAC#TXBUFERR
Tmacdck_ERROR Data Setup PHYEMAC#TXBUFERR
Clock To Out:
Tmaccko_COMMA Data Output EMAC#PHYENCOMMAALIGN
Tmaccko_LOOPBACK Data Output EMAC#PHYLOOPBACKMSB
Tmaccko_RESET Data Output EMAC#PHYMGTTXRESET
Tmaccko_POWER Data Output EMAC#PHYPOWERDOWN
Tmaccko_SYNC Data Output EMAC#PHYSYNCACQSTATUS
Tmaccko_DISP Data Output EMAC#PHYTXCHARDISPMODE
Tmaccko_DISP Data Output EMAC#PHYTXCHARDISPVAL
Tmaccko_CHAR Data Output EMAC#PHYTXCHARISK
Tabl e A - 5 : PHYEMAC#MIITXCLK Switching Characteristics
Parameter Function Signal
Clock To Out:
Tmaccko_TXCLK Data Output EMAC#PHYTXCLK
Tmaccko_TXD Data Output EMAC#PHYTXD
Tmaccko_EN Data Output EMAC#PHYTXEN
Tmaccko_ERROR Data Output EMAC#PHYTXER
Tabl e A - 6 : PHYEMAC#RXCLK Switching Characteristics
Parameter Function Signal
Setup and Hold Relative to Clock:
Tmacckd_COL Data Hold PHYEMAC#COL
Tmacdck_COL Data Setup PHYEMAC#COL
Tmacckd_CRS Data Hold PHYEMAC#CRS
Tmacdck_CRS Data Setup PHYEMAC#CRS
Tmacckd_RXD Data Hold PHYEMAC#RXD
Tmacdck_RXD Data Setup PHYEMAC#RXD
Tmacckd_VALID Data Hold PHYEMAC#RXDV
Tmacdck_VALID Data Setup PHYEMAC#RXDV
Tmacckd_ERROR Data Hold PHYEMAC#RXER
Tabl e A - 4 : PHYEMAC#GTXCLK Switching Characteristics (Cont’d)
Parameter Function Signal
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English