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Xilinx Virtex-4 - Transmit (TX) Client - 16-Bit Wide Interface

Xilinx Virtex-4
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 47
UG074 (v2.2) February 22, 2010
Client Interface
R
Transmit (TX) Client – 16-bit Wide Interface
This optional configuration can only be used when the Ethernet MAC is configured in
1000BASE-X PCS/PMA mode. The frequency of the transmit client clock is half the
frequency of the internal transmit. The 16-bit client interface allows the Ethernet MAC to
run at an internal clock frequency of greater than 125 MHz. The Ethernet MAC can run at
a line rate greater than 1 Gb/s as specified in IEEE Std 802.3. Therefore, this interface
should not be used for Ethernet compliant designs, but it can be useful for backplane
applications.
The PHYEMAC#MIITXCLK is used as the input clock port for the
CLIENTEMAC#TXCLIENTCLKOUT, divided by two, as shown in Figure 3-1, page 38.
Using a DCM with the transmit client clock (EMACCLIENT#TXCLIENTCLKOUT) as an
input, the divide-by-two clock signal is generated. See Figure 4-28, page 139 for more
information.
As in the 8-bit client interface, the PCS engine inserts code characters in the data stream
from CLIENTEMAC#TXD. Table 3-1 describes these code characters, and IEEE Std 802.3,
Clause 36 has further definitions. CLIENTEMAC#TXD[7:0] is transmitted to
EMAC#PHYTXD first. Along with EMAC#PHYTXCHARISK and
EMAC#PHYTXCHARDISPMODE, the MGT encodes the incoming data to the appropriate
8B/10B stream.
Figure 3-11 shows the timing of a normal outbound frame transfer for the case with an
even number of bytes in the frame.
Figure 3-10: IFG Adjustment
DA SA
CLIENTEMAC#TXIFGDELAY
IFG ADJUST VALUE
0x0D
13 Idles Inserted
DA
Next IFG
ADJUST VALUE
ug074_3_12_101004
CLIENTEMAC#TXCLIENTCLKIN
CLIENTEMAC#TXD[7:0]
CLIENTEMAC#TXDVLD
EMAC#CLIENTTXACK
CLIENTEMAC#TXFIRSTBYTE
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