Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 39
UG074 (v2.2) February 22, 2010
Client Interface
R
Figure 3-2 shows a block diagram of the receive client interface. In 16-bit client mode,
PHYEMAC#RXCLK functions as CLIENTEMAC#RXCLIENTCLKIN/2.
TIEEMAC#CONFIGVEC[65] selects between an 8-bit or 16-bit client interface.
Table 3-1 defines the abbreviations used throughout this chapter.
Figure 3-2: Receive Client Interface Block Diagram
Receive
Engine
Receive
Client
Interface
PHYEMAC#RXCLK
PHYEMAC#RXDV
PHYEMAC#RXD[7:0]
PHYEMAC#RXER
RX_DATA_VALID
(Internal Signal)
RX_CLK
(Internal Signal)
RX_DATA[7:0]
(Internal Signal)
RX_GOOD_FRAME
(Internal Signal)
RX_BAD_FRAME
(Internal Signal)
Ethernet MAC Block
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXD[15:0]
EMAC#CLIENTRXDVLDMSW
PHYEMAC#RXCLK
CLIENTEMAC#RXCLIENTCLKIN
CLIENT PHY
FPGA Fabric
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
CLIENTEMAC#RXCLIENTCLKIN
TIEEMAC#CONFIGVEC[65]
ug074_3_04_070105
Table 3-1: Abbreviations Used in this Chapter
Abbreviation Definition Length
DA Destination address 6 bytes
SA Source address 6 bytes
L/T Length/Type field 2 bytes
FCS Frame check sequences 4 bytes
SGMII and 1000BASE-X PCS/PMA Only:
PRE Preamble 7 bytes
SFD Start of frame delimiter 1 byte
/I1/ IDLE_1 (K28.5/D5.6) 2 bytes
/I2/ IDLE_2 (K28.5/D16.2) 2 bytes
/R/ Carrier Extend (K23.7) 1 byte
/S/ Start of Packet (K27.7) 1 byte
/T/ End of Packet (K29.7) 1 byte
/V/ Error Propagation (K30.7) 1 byte
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English