Xilinx Virtex-4 User Manual

38 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
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Figure 3-1: Transmit Client Block Diagram
Transmit
Engine
Transmit
Client
Interface
EMAC#PHYTXCLK
EMAC#PHYTXEN
EMAC#PHYTXD[7:0]
EMAC#PHYTXER
TX_DATA_VALID
(Internal Signal)
TX_DATA[7:0]
(Internal Signal)
TX_COLLISION
(Internal Signal)
TX_RETRANSMIT
(Internal Signal)
Ethernet MAC Block
CLIENTEMAC#TXDVLD
CLIENTEMAC#TXD[15:0]
CLIENTEMAC#TXDVLDMSW
PHYCLIENT
PHYEMAC#GTXCLK
TIEEMAC#CONFIGVEC[66]
CLIENTEMAC#TXCLIENTCLKIN
PHYEMAC#MIITXCLK
TX_ACK
(Internal signal)
TX_ACK_EARLY
(Internal Signal)
TX_UNDERRUN
(Internal Signal)
TX_IFG_DELAY[7:0]
(Internal Signal)
EMAC#CLIENTTXACK
EMAC#CLIENTTXRETRANSMIT
EMAC#CLIENTTXCOLLISION
CLIENTEMAC#TXIFGDELAY[7:0]
CLIENTEMAC#TXUNDERRUN
CLIENTEMAC#TXFIRSTBYTE
TXFIRSTBYTEREG
(Internal Signal)
FPGA Fabric
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074_3_03_070105
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English