Xilinx Virtex-4 - GMII Clock Management

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 107
UG074 (v2.2) February 22, 2010
Gigabit Media Independent Interface (GMII) Signals
R
GMII Clock Management
1 Gb/s GMII Only
Figure 4-7 shows GMII clock management when using one Ethernet MAC. The GTX_CLK
has a frequency of 125 MHz. GTX_CLK must be provided to the Ethernet MAC. This is a
high quality 125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements.
The EMAC#CLIENTTXGMIIMIICLKOUT output port drives all of the transmit logic
through a BUFG. The output of the BUFG connects to:
• GMII_TXD registers in the FPGA fabric
• Input port CLIENTEMAC#TXGMIIMIICLKIN
• CLIENTEMAC#TXCLIENTCLKIN
• TX client logic
PHYEMAC#MIITXCLK must be tied to ground. The GMII_RX_CLK_# is generated from
the PHY and is connected to PHYEMAC#RXCLK through a DCM and a BUFG. The
CLIENTEMAC#DCMLOCKED port must be tied High. The DCM is used to shift the
received GMII clock with respect to the data, in order to sample a 2 ns setup, 0 ns hold
window at the device pads. Phase shifting is applied to the DCM to fine tune the setup and
i
Figure 4-7: 1 Gb/s GMII Clock Management
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#DCMLOCKED
PHYEMAC#RXCLK
EMAC#PHYTXD[0]
PHYEMAC#RXD[0]
PHYEMAC#MIITXCLK
EMAC#
GTX_CLK
TX CLIENT
LOGIC
RX CLIENT
LOGIC
BUFG
OBUF
GMII_TXD_#[0]
QD
GND
NC
NC
UG074_3_53_031009
OBUF
ODDR
GMII_TX_CLK_#
D1
D2
0
1
GMII_RXD_#[0]
GMII_RX_CLK_#
IBUF
IBUFG
BUFG
QD
CLK0
CLKIN
CLKFB
DCM
www.BDTIC.com/XILINX