Xilinx Virtex-4 User Manual

122 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
R
RGMII Signals
An Ethernet MAC wrapper has all necessary pin connections to configure the primitive
into RGMII. Table 4-3 describes the 10/100/1000 RGMII interface signals.
Table 4-3: 10/100/1000 RGMII Interface Signals
Signal Direction Description
GTX_CLK Input
The transmit clock at 125 MHz. The clock timing and characteristics
meet the IEEE Std 802.3-2002 specification. Other transmit clocks are
derived from this clock.
RGMII_TXC_# Output Transmits clock out to the PHY.
RGMII_TXD_# Output
Transmits the first 4 bits of packet data ([3:0]) on the rising edge of
RGMII_TXC_#, and the top 4 bits ([7:4]) on the falling edge. TXD is 4 bits
wide connecting to the PHY.
RGMII_TX_CTL_#
(1)
Output
This signal is TXEN on the rising edge of RGMII_TXC_#, and an
encoded TXERR on the falling edge.
RGMII_RXC_# Input
Recovered clock from data stream by the PHY: 125 MHz, 25 MHz or
2.5 MHz.
RGMII_RXD_# Input
Receives the lower 4 bits of packet data ([3:0]) on the rising edge, and the
upper 4 bits of packet data ([7:4]) on the falling edge of RGMII_RXC_#.
RGMII_RX_CTL_#
(1)
Input
This signal is RXDV on the rising edge of RGMII_RXC_#, and an
encoded RXERR on the falling edge.
Notes:
1. See the Hewlett Packard RGMII specification v1.3 or v2.0 (section 3.4) for more information.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English