Xilinx Virtex-4 - Page 121

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 121
UG074 (v2.2) February 22, 2010
10/100/1000 RGMII
R
Figure 4-16: Tri-Mode RGMII v1.3 Clock Management
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#PHYTXD[3:0]
EMAC#
GTX_CLK
BUFG
TX Client
Logic
BUFG
RX Client
Logic
OBUF
RGMII_TXD_#[3:0]
QD1
PHYEMAC#MIITXCLK
ODDR
D2EMAC#PHYTXD[7:4]
QD1
ODDR
D2
OBUF
RGMII_TXC_#
1
0
CLIENTEMAC#DCMLOCKED
UG074_3_67_031009
BUFG
(1)
PHYEMAC#RXCLK
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
Notes:
1) A regional buffer (BUFR) can replace this BUFG.
Refer to the Virtex-4 User Guide for BUFR usage guidelines.
CLKIN
CLKFB
DCM
CLK0
RGMII_RXD_#[3:0]
SPEED_IS_10_100
IBUF
BUFGMUX
Q1
Q2
D
RGMII_RXC_#
IBUFG
0
1
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