Xilinx Virtex-4 User Manual

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 153
UG074 (v2.2) February 22, 2010
Auto-Negotiation Interrupt
R
• The PHY then passes the results of the auto-negotiation process with the link partner
to the Ethernet 1000BASE-X PCS/PMA or SGMII (in SGMII mode), by leveraging the
1000BASE-X auto-negotiation specification shown in Figure 5-3. This transfers the
results of the Link Partner auto-negotiation across the SGMII and this is the only auto-
negotiation observed by the sub-layer.
The SGMII auto-negotiation function leverages the 1000BASE-X PCS/PMA auto-
negotiation function with the exception of:
• The duration of the Link Timer of the SGMII auto-negotiation decreases from 10 ms to
1.6 ms making the entire auto-negotiation cycle faster (see “Auto-Negotiation Link
Timer,” page 153).
• The information exchanged now contains speed resolution in addition to duplex
mode.
The results of SGMII auto-negotiation can be used as described in “1000BASE-X Auto-
Negotiation Overview,” page 151.
Auto-Negotiation Link Timer
The built-in auto-negotiation Link Timer has different durations for different standards.
1000BASE-X Standard
The 1000BASE-X standard Link Timer is defined as having a duration somewhere between
10.354 ms and 10.387 ms.
SGMII Standard
The SGMII standard Link Timer is defined as having a duration of 1.606 ms to 1.638 ms.
Using the Auto-Negotiation Interrupt
The auto-negotiation function has an EMAC#CLIENTANINTERRUPT port. This port is
designed to be used with common microprocessor bus architectures (for example, the
CoreConnect™ bus interfacing to a MicroBlaze design or the PPC405 processor
implemented in the Virtex-4 device).
The operation of this port is enabled or disabled and cleared via Register 16 (see Table 4-19,
“Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16)”).
• When disabled, this port is permanently driven Low.
• When enabled, this port is set to logic 1 following the completion of an auto-
negotiation cycle. It remains high until cleared after a zero is written to bit 16.1
(Interrupt Status bit) of Register 16.
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English

Summary

Chapter 1 Introduction

Features

Lists the key features and capabilities of the Virtex-4 FPGA Ethernet MAC.

Chapter 2 Ethernet MAC Architecture

Ethernet MAC Signal Descriptions

Defines and categorizes all signals of the Ethernet MAC primitive.

Chapter 3 Client, Host, and MDIO Interfaces

Client Interface

Explains the client interface design for flexibility in matching switching fabric or network processor interfaces.

Host Interface

Describes how to access Ethernet MAC registers and statistics via the host interface.

Chapter 4 Physical Interface

10/100/1000 Serial Gigabit Media Independent Interface (SGMII)

Explains the SGMII interface, its RX elastic buffer options, and clock management.

1000BASE-X PCS/PMA

Covers the 1000BASE-X PCS/PMA interface, its functional blocks, and clock management.

Chapter 6 Use Models

Interfacing to the Processor DCR

Shows sample code for accessing Ethernet MAC registers via the processor's DCR bus.

Interfacing to an FPGA Fabric-Based Statistics Block

Explains how to integrate Ethernet MAC statistics with a LogiCORE Statistics block via host bus or DCR bus.

Chapter 7 Using the Embedded Ethernet MAC

Accessing the Ethernet MAC from the CORE Generator tool