Xilinx Virtex-4 User Manual

152 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 5: Miscellaneous Functions
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2. During auto-negotiation, the contents of Register 4 (see Table 4-13, “Auto-Negotiation
Advertisement Register (Register 4)”) are transferred to the link partner. This register
can be written through the management interface, and enables software control of the
system’s advertised abilities. Information provided in this register includes:
♦ Fault condition signalling
♦ Duplex mode
♦ Flow control capabilities for the attached Ethernet MAC.
3. At the same time, the advertised abilities of the Link Partner are transferred into
Register 5 (see Table 4-14, “Auto-Negotiation Link Partner Ability Base Register
(Register 5)”). This includes the same information as in Register 4.
4. Under normal conditions, this completes the auto-negotiation information exchange.
It is now the responsibility of system management (for example, software running on
an embedded PowerPC or MicroBlaze device) to complete the cycle. The results of the
auto-negotiation should be read from Register 5, and other networking components,
such as an attached Ethernet MAC, should be configured accordingly. There are two
methods by which a host processor may learn of the competition of an auto-
negotiation cycle:
♦ By polling the auto-negotiation completion bit 1.5 in Register 1 (see Table 4-11,
“Status Register (Register 1)”).
♦ By using the auto-negotiation interrupt port (see “Using the Auto-Negotiation
Interrupt,” page 153).
SGMII Standard
Figure 5-4 illustrates the operation of SGMII auto-negotiation.
The SGMII capable PHY has two distinctive sides to auto-negotiation:
• The PHY performs auto-negotiation with its link partner using the relevant auto-
negotiation standard for the chosen medium (BASE-T auto-negotiation, illustrated in
Figure 5-4, uses a twisted copper pair medium). This resolves the operational speed
and duplex mode with the link partner.
Figure 5-4: SGMII Auto-Negotiation Overview
Ethernet 1000BASE-X
PCS/PMA or SGMII
Sub-Layer
Virtex-4 FPGA
Ethernet
Media
Access
Controller
PowerPC/
MicroBlaze
Processors
Host Interface
EMAC#CLIENTANINTERRUPT
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg5)
SGMII capable
BASE-T PHY
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg5)
SGMII
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg5)
SGMII side
BASE-T side
Tw i sted
Copper
Pair
Link Partner
Auto-Neg Adv
(Reg 4)
Link Partner Ability
Base (Reg5)
ug074_3_66_080805
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Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English