Xilinx Virtex-4 - Pinout Guidelines

156 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 6: Use Models
R
Pinout Guidelines
Xilinx recommends the following guidelines to improve design timing using the Virtex-4
FPGA Embedded Tri-Mode Ethernet MAC:
• If available, use dedicated global clock pins for the Ethernet MAC input clocks.
• Use the column of IOBs located closest to the PowerPC processor and Ethernet MAC
block.
• Use the MGTs located closest to the PowerPC processor and Ethernet MAC block.
www.BDTIC.com/XILINX