Name: Xilinx Virtex-4
Brand: Xilinx
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Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 161

UG074 (v2.2) February 22, 2010

Interfacing to an FPGA Fabric-Based Statistics Block

// Write the PHY address and PHY register to be accessed to the

// dataRegLSW register

mtdcr(0x0 + 13, 0x00000020);

// Write the decode address for MDIO address output to the cntlReg

// register

mtdcr(0x0 + 14, 0x87B4);

// Poll the RDYstatus register

while ( !(mfdcr(0x0 + 15) & 0x00000400) );

Interfacing to an FPGA Fabric-Based Statistics Block

When the Ethernet MAC Is Implemented with the Host Bus

When the Ethernet MAC is used with the host bus, interfacing to a fabric-based statistics

block is straight forward. Statistics information is passed from the Ethernet MAC via the

statistics vectors EMAC#CLIENTTXSTATS and EMAC#CLIENTRXSTATS. The statistics

values can then be read via a host interface, shared between the statistics counters and the

Ethernet MAC block.

To share the host bus without contention, statistics counters need to use a different address

space than the Ethernet MAC configuration registers. Conflicts with MDIO register access

are avoided by only accessing statistics counters when the signal HOSTMIIMSEL is at

logic 0. Implementation of the addressing scheme shown in Table 6-1 ensures that the host

bus can be shared without contention. This scheme provides space to address 512 statistics

counters per Ethernet MAC, using addresses 0x000 to 0x1FF.

Figure 6-1 shows how to integrate the Ethernet MAC with the LogiCORE Ethernet

Statistics block, where the Ethernet statistics counters are accessed via the host bus. The

LogiCORE Ethernet Statistics block is used with the addressing scheme shown in

Table 6-1. DS323

, LogiCORE Ethernet Statistics Data Sheet, provides a a full description of

the Ethernet Statistics LogiCORE block. Figure 6-1 illustrates how to connect Ethernet

Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If statistics are

required for only one Ethernet MAC, then the multiplexing between the statistics cores is

simply replaced with a straight-through connection.

Table 6-1: Addressing Scheme

Transaction Host_miim_sel Host_addr[9]

Configuration 01

MIIM Access 1X

Statistics Access 00

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