Xilinx Virtex-4 User Manual

98 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 3: Client, Host, and MDIO Interfaces
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In MDIO transactions, the following applies:
• HOSTOPCODE maps to the OPCODE field of the MDIO frame.
• HOSTADDR maps to the two address fields of the MDIO frame; PHY_ADDR is
HOSTADDR[9:5], and REG_ADDR is HOSTADDR[4:0].
• HOSTWRDATA[15:0] maps into the data field of the MDIO frame during a write
operation.
• The data field of the MDIO frame maps into HOSTRDDATA[15:0] during a read
operation.
The Ethernet MAC signals to the host that it is ready for an MDIO transaction by asserting
HOSTMIIMRDY. A read or write transaction on the MDIO is initiated by a pulse on the
HOSTREQ signal. This pulse is ignored if the MDIO interface already has a transaction in
progress. The Ethernet MAC deasserts the HOSTMIIMRDY signal while the transaction
across the MDIO is in progress. When the transaction across the MDIO interface is
completed, the HOSTMIIMRDY signal is asserted by the Ethernet MAC. If the transaction
is a read, the data is also available on the HOSTRDATA[15:0] bus.
As noted in Figure 3-52, if a read transaction is initiated, the HOSTRDDATA bus is valid at
the point indicated. If a write transaction is initiated, the HOSTWRDATA bus must be
valid at the point indicated. Simultaneous read and write is not permitted.
For register map details of the physical layer devices and a complete description of the
operation of the MDIO interface itself, see IEEE specification 802.3-2002.
Figure 3-52: MDIO Access Through the Management Interface
HOSTCLK
HOSTADDR[9:0]
HOSTOPCODE[1:0]
HOSTREQ
HOSTMIIMSEL
HOSTRDDATA[15:0]
HOSTWRDATA[15:0]
HOSTMIIMRDY
ug074_3_46_080805
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Xilinx Virtex-4 Specifications

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Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English