Xilinx Virtex-4 - Page 111

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 111
UG074 (v2.2) February 22, 2010
Gigabit Media Independent Interface (GMII) Signals
R
Figure 4-10: Tri-Mode GMII Clock Management with Byte PHY Enabled
EMAC#
PHYEMAC#GTXCLK
CLIENTEMAC#TXGMIIMIICLKIN
EMAC#CLIENTTXGMIIMIICLKOUT
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
EMAC#PHYTXD[3:0]
EMAC#PHYTXD[7:4]
PHYEMAC#MIITXCLK
PHYEMAC#RXCLK
PHYEMAC#RXD[3:0]
PHYEMAC#RXD[7:4]
CLIENTEMAC#DCMLOCKED
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
GTX_CLK
TX Client
Logic
RX Client
Logic
OBUFODDR
D1
D2
Q
Q
GMII_TXD_#[3:0]
GMII_RXD_#[3:0]
BUFGMUX
D
ODDR
D1
D2
Q
OBUF
GMII_TXD_#[7:4]
IBUFG
MII_TX_CLK_#
SPEED_IS_10_100
SPEED_IS_10_100
I0
I1
I0
I1
BUFGMUX
SPEED_IS_10_100
I0
I1
Q
D
Q
IBUF
GMII_RXD_#[7:4]
D
D
Q1
IDDR
IDDR
Q2
Q1
Q2
4-bit to 8-bit
Realignment
Logic
rx_clk_div2
tx_clk_div2
X
X
UG074_3_77_031009
IBUF
OBUF
ODDR
GMII_TX_CLK_#
D1
D2
0
1
CLKIN
CLKFB
DCM
CLK0
GMII_RX_CLK_#
IBUFG
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