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Xilinx Virtex-4 User Manual
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.xilinx.com
Embedded T
ri-Mode Ether
net MAC User Guide
UG074 (v2.2) F
ebr
uar
y 22, 2010
Chapter 4:
Physica
l Interface
R
Figure 4-27:
1000BASE-X PCS/PMA (8-bit Da
ta Client) Clock Manag
ement
UG074_3_80_030907
GT11
GT11CLK_MGT
MGTCLKP
MGTCLKN
S
YNCLK1OUT
REFCLK1
RXU
S
RCLK2
RXU
S
RCLK
‘0’
250 MHz
BUFG
TXU
S
RCLK2
TXOUTCLK1
TXU
S
RCLK
‘0’
EMA
C#
PHYEMA
C#GTXCLK
CLIENTEMA
C#TXCLIENTCLKIN
EMA
C#CLIENTTXCLIENTCLK
OUT
CLIENTEMA
C#RXCLIENTCLKIN
EMA
C#CLIENTRXCLIENTCLK
OUT
Client
Logic
X
X
www.BDTIC.com/XILINX
137
139
Table of Contents
Default Chapter
9
Table of Contents
9
Preface: about this Guide
13
Guide Contents
13
Additional Resources
13
Conventions
14
Typographical
14
Online Document
14
Chapter 1: Introduction
15
Ethernet MAC Overview
15
Features
16
Chapter 2: Ethernet MAC Architecture
17
Architecture Overview
17
Ethernet MAC Primitive
20
Ethernet MAC Signal Descriptions
22
Client Signals
22
Clock Signals
25
Host Interface Signals
26
Reset and CLIENTEMAC#DCMLOCKED Signals
27
Tie-Off Pins
28
Management Data Input/Output (MDIO) Interface Signals
32
Mode-Dependent Signals
32
Rocketio Multi-Gigabit Transceiver Signals
34
Chapter 3 : Client, Host, and MDIO Interfaces
37
Client Interface
37
Transmit (TX) Client - 8-Bit Wide Interface
40
Transmit (TX) Client - 16-Bit Wide Interface
47
Receive (RX) Client - 8-Bit Wide Interface
51
Receive (RX) Client - 16-Bit Wide Interface
56
Address Filtering
58
Flow Control Block
61
Statistics Vector
65
Host Interface
72
Host Clock Frequency
74
Configuration Registers
74
Address Filter Registers
80
Using the DCR Bus as the Host Bus
83
Description of Ethernet MAC Register Access through the DCR Bus
89
Address Code
91
MDIO Interface
93
Introduction to MDIO
93
MDIO Implementation in the EMAC
95
Accessing MDIO Via the EMAC Host Interface
97
Chapter 4: Physical Interface
99
Media Independent Interface (MII)
99
MII Interface
99
MII Clock Management
101
MII Signals
104
Gigabit Media Independent Interface (GMII) Signals
105
GMII Interface
105
GMII Clock Management
107
Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)
110
GMII Signals
112
10/100/1000 Rgmii
113
Gb/S RGMII Interface
113
Gb/S RGMII Clock Management
115
Tri-Mode RGMII V2.0
117
Tri-Mode RGMII V1.3
120
RGMII Signals
122
10/100/1000 Serial Gigabit Media Independent Interface (SGMII)
123
SGMII RX Elastic Buffer
123
10/100/1000 SGMII Interface
130
10/100/1000 SGMII Clock Management
131
SGMII Signals
132
Management Registers
134
1000Base-X Pcs/Pma
135
1000BASE-X PCS/PMA Interface
135
Shim
137
1000BASE-X PCS/PMA Clock Management
137
PCS/PMA Signals
140
Management Registers
140
Chapter 5: Miscellaneous Functions
147
Clock Frequency Support
147
Transmit Clocking Scheme
148
Receive Clocking Scheme
149
Ethernet MAC Configuration
149
Auto-Negotiation Interrupt
151
Overview of Operation
151
Auto-Negotiation Link Timer
153
Using the Auto-Negotiation Interrupt
153
Chapter 6: Use Models
155
Simulation Models
155
Secureip Model
155
Model Considerations
155
Pinout Guidelines
156
Interfacing to the Processor DCR
157
Interfacing to an FPGA Fabric-Based Statistics Block
161
When the Ethernet MAC Is Implemented with the Host Bus
161
When the Ethernet MAC Is Implemented with the DCR Bus
163
Chapter 7: Using the Embedded Ethernet MAC
167
Accessing the Ethernet MAC from the CORE Generator Tool
167
Simulating the Ethernet MAC Using the Ethernet MAC Wrappers
167
Appendix A: Ethernet MAC Timing Model
169
Timing Parameters
169
Input Setup/Hold Times Relative to Clock
169
Clock to Output Delays
170
Core Latency
170
Timing Diagram and Timing Parameter Tables
171
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Xilinx Virtex-4 Specifications
General
Brand
Xilinx
Model
Virtex-4
Category
Motherboard
Language
English
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