Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 19
UG074 (v2.2) February 22, 2010
Architecture Overview
R
Figure 2-2: Functional Block Diagram of 10/100/1000 Ethernet MAC
Clock Management
Transmit Engine
Flow Control
Receive Engine
Statistics
Host
Interface
Generic
Host Bus
DCR Bus
TX
RX
MDIO Interface
to External PHY
MDIO Interface
Address Filter Registers
MGT
MII / GMII / RGMII Interface
to External PHY
16-bit or 8-bit Client Interface
MII / GMII / RGMII Interface
PCS / PMA Sublayer
Configuration Registers
UG074_2_02_081308
tx_stats_vec rx_stats_vec