Xilinx ZC702 User Manual

ZC702 Board User Guide www.xilinx.com 22
UG850 (v1.7) March 27, 2019
Feature Descriptions
The configuration and Quad SPI section of the Zynq-7000 SoC Technical Reference Manual
(UG585) [Ref 2] provides details on using the Quad-SPI flash memory.
Figure 1-6 shows the connections of the linear Quad SPI flash memory on the ZC702 board.
For more details, see the Micron N25Q128A11ESF40G data sheet at the Micron website
[Ref 14].
USB 2.0 ULPI Transceiver
[Figure 1-2, callout 4]
The ZC702 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI
Transceiver at U9 to support a USB connection to the host computer. A USB cable is
supplied in the ZC702 Evaluation Kit (Standard-A connector to host computer, Mini-B
connector to ZC702 board connector J1). The USB3320 is a high-speed USB 2.0 PHY
supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard
defines the interface between the USB controller IP and the PHY device which drives the
physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB
controller IP and the PHY device.
PS_MIO3 500 F6 QSPI_IO1
8 DQ1 J20.2
PS_MIO2 500 A2 QSPI_IO0
15 DQ0 J21.2
PS_MIO1 500 A1 QSPI_CS_B
7S_BNA
Notes:
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
Table 1-5: Quad SPI Flash Memory Connections to the XC7Z020 SoC (C ont’d)
XC7Z020 (U1)
Schematic
Net Name
Quad-SPI Flash Memory (U41)
MIO Select
Header
Pin Name Bank Pin Number Pin Number Pin Name
X-Ref Target - Figure 1-6
Figure 1-6: 128 Mb Quad-SPI Flash Memory (U41)
UG850_c1_06_032719
N25Q128A11ESF40G
128 Mb Serial
Flash Memory
GND
1
2
3
5
7
6
U41
4
8
VCCMIO
C23
0.1μF 25V
X5R
QSPI_IO2
DQ1
16
15
14
12
10
11
13
9
SB
NC3
NC2
NC1
NC0
VCC
HOLD_B/DQ3
WB/VPP/DQ2
VSS
NC4
NC5
NC6
NC7
DQ0
C
QSPI_IO0
QSPI_CLK
GND
R324
330Ω 5%
QSPI_IO3
QSPI_IO1
QSPI_CS_B
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Xilinx ZC702 Specifications

General

Brand	Xilinx
Model	ZC702
Category	Motherboard
Language	English