Xilinx ZC702 - GPIO DIP Switch

ZC702 Board User Guide www.xilinx.com 48
UG850 (v1.7) March 27, 2019
Feature Descriptions
GPIO DIP Switch
[Figure 1-2, callout 19]
Figure 1-23 shows the GPIO DIP switch circuit.
Table 1-25 lists the GPIO DIP switch connections to XC7Z020 SoC U1.
X-Ref Target - Figure 1-23
Figure 1-23: GPIO DIP Switch
Table 1-25: GPIO DIP Switch Connections to XC7Z020 SoC at U1
XC7Z020 (U1) Pin Net Name I/O Standard DIP Switch SW12 Pin
W6 GPIO_DIP_SW0 LVCMOS25 2
W7 GPIO_DIP_SW1 LVCMOS25 1
UG850_c1_23_032719
SDA02H1SBD
SW12
VADJ
4
3
GPIO_DIP_SW1
GPIO_DIP_SW0
R51
4.7kΩ
0.1
Ω
5%
R50
4.7kΩ
0.1
Ω
5%
GND
1
2
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