52
RX-A4A
Pin
No.
Port Name Function Name
I/O
Detail of FunctionRelated Power Supply
OFF ON
76 PW1/TSPI8SCK/T32A00OUTA/T32A00OUTC EX_SCK AC O O EEPROM/LCD Module Communication Clock
77 PW0/TSPI8CS0/T32A00OUTB/TSPI8CSIN EEP_N_CS AC I O
EEPROM Chip Select
When it is dropped to Low, the EEPROM becomes
Active, so Input at AC Off (Pushed at +3.3M)
78
PV7/T32A05OUTB/TSPI5CS0/OVV0/TSPI5CSIN/
UT1RTS_N
SPI_BUSSW_EN AC O O
Control Signal of SPI BUS SW Directly Connected to
WN-QCS
79
PV6/T32A05OUTA/T32A05OUTC/TSPI5SCK/
EMG0/UT1CTS_N
WN_SPI_SCK WN_PON O O Network CPU SPI Communication Clock
80
PV5/T32A04OUTA/T32A04OUTC/TSPI5TXD/ZO0/
I2C2SDA/UT1TXDA
WN_SPI_MOSI WN_PON O O Network CPU SPI Transmit Data
81
PV4/T32A04OUTB/TSPI5RXD/WO0/I2C2SCL/
UT1RXD
WN_SPI_MISO WN_PON I I Network CPU SPI Receive Data
82
PM7/T32A07OUTB/I2C4SCL/FUT1IROUT/
TSPI7TXD/FUT1TXD
DSP_MOSI DSP2_PON O O DSP / DIR / Audio FPGA Transmit data
83
PM6/T32A07OUTA/T32A07OUTC/I2C4SDA/
FUT1IRIN/TSPI7RXD/FUT1RXD
DSP_MISO DSP2_PON I I DSP / DIR / Audio FPGA Receive data
84
PM5/T32A06OUTA/T32A06OUTC/TSPI7SCK/
FUT1RTS_N
DSP_SCK DSP2_PON O O
DSP / DIR / Audio FPGA Communication Clock
Keep Low for at least 20 ns before and after DSP reset
release
(Involved in DSP boot mode)
85
PM4/INT15b/T32A06OUTB/TSPI7CSIN/TSPI7CS0/
FUT1CTS_N
DSP2_N_CS DSP2_PON O O DSP2 Chip Select (D81Y)
86 PH7/TRST_N/UT0CTS_N/UT0RTS_N DSP2_N_SPIRDY DSP2_PON O I DSP2 SPI Ready (D81Y)
87 PH6/TDO/SWV/UT0RTS_N/UT0CTS_N --- --- --- --- Serial Wire Debug Port
88 PH5/TCK/SWCLK/UT0TXDA/UT0RXD --- --- --- --- Serial Wire Debug Port
89 PH4/TMS/SWDIO/UT0RXD/UT0TXDA --- --- --- --- Serial Wire Debug Port
90 PH3/TDI/UT1CTS_N/NBD0SYNC/UT1RTS_N --- AC O O No Use
91
PH2/TRACEDATA3/UT1RTS_N/NBD0DATA3/
UT1CTS_N
DIR_N_RST DSP2_PON O O DIR Reset
92
PH1/TRACEDATA2/UT1TXDA/NBD0DATA2/
UT1RXD
WN_MOSI WN_PON O O Network CPU UART Transmit Data
93
PH0/TRACEDATA1/UT1RXD/NBD0DATA1/
UT1TXDA
WN_MISO WN_PON I I Network CPU UART Receive Data
94 PG7/TRACEDATA0/NBD0DATA0/FUT0CTS_N DIR1_N_CS DSP2_PON O O DIR1 Chip Select
95
PG6/TRACECLK/NBD0CLK/FUT0RTS_N
DIR2_N_CS DSP2_PON O O DIR2 Chip Select
96
PG5/T32A02OUTA/T32A02OUTC/FUT0IRIN/
FUT0RXD/I2C2SCL
EX_SCL AC O O Tuner/Touch Sensor I2C Clock
97
PG4/T32A02OUTB/FUT0IROUT/FUT0TXD/
I2C2SDA
EX_SDA AC O I/O Tuner/Touch Sensor I2C Data
98 DVDD3E --- --- --- --- ---
99 DDVSSE --- --- --- --- ---
100
PL3/T32A02INB0/T32A02INC1/TSPI3CS1/
TSPI1TXD
DSP1_SPI_MISO DSP1_PON O O SPI MISO of SOC (Microprocessor: slave)
101 PL2/TSPI1RXD DSP1_SPI_MOSI DSP1_PON I I SPI MOSI of SOC (Microprocessor: slave)
102 PL1/TSPI1SCK DSP1_SPI_SCK DSP1_PON I I SPI Clock of SOC (Microprocessor: slave)
103
PL0/INT01a/T32A02INA0/T32A02INC0/TSPI1CSIN/
TSPI1CS0
DSP2_N_RST DSP2_PON O O DSP2 Reset (D81Y)
104
PK7/INT00a/T32A01INB0/T32A01INC1/TSPI3CS0/
SMI0CS0_N/TSPI3CSIN
SF_N_CS
DFF_FROM_N_
RST
O S Flash ROM Chip Select
105
PK6/TSPI1CS3/T32A01INA0/T32A01INC0/
TSPI3SCK/SMI0CLK
SF_SCK
DFF_FROM_N_
RST
O S Flash ROM Clock
106 PK5/TSPI1CS2/TSPI3RXD/SMI0D3 SF_IO3
DFF_FROM_N_
RST
O S Flash ROM Data3
Pin
No.
Port Name Function Name
I/O
Detail of FunctionRelated Power Supply
OFF ON
107 PK4/TSPI1CS1/TSPI3TXD/SMI0D2 SF_IO2
DFF_FROM_N_
RST
O S Flash ROM Data2
108 PK3/ECS1_N/SMI0D1 SF_IO1
DFF_FROM_N_
RST
O S Flash ROM Data1
109 PK2/ECS0_N/SMI0D0 SF_IO0
DFF_FROM_N_
RST
O S Flash ROM Data0
110
PK1/INT11a/ISDBOUT/T32A00INB0/T32A00INC1/
HDMAREQB
HAU2_N_INT HDMI_PON O I
HDMI SW (ZONE) Audio Mute Interrupt 2 (MN864 ***
NIRQA1)
111
PK0/INT10a/ISDAOUT/T32A00INA0/T32A00INC0/
SMI0CS1_N
HAU_N_INT HDMI_PON O I
HDMI RTX (ZONE) Audio Mute Interrupt 1
(MN864***,*** NIRQA0)
112
PV3/T32A09OUTB/ISDBIN3/YO0/UT3CTS_N/
UT3RTS_N
ARC_N_RST HDMI_PON O O eARC Reset
113
PV2/T32A09OUTA/T32A09OUTC/ISDBIN2/VO0/
UT3RTS_N/UT3CTS_N
HSW1_N_INT HDMI_PON O I HDMI Switcher Interrupt (MN864807 NIRQ1)
114
PV1/T32A09INB0/T32A09INC1/ISDBIN1/XO0/
UT3TXDA/UT3RXD
MT_DA DSP2_PON O O Mute Digital Audio(DSP2)
115
PV0/T32A09INA0/T32A09INC0/ISDBIN0/UO0/
UT3RXD/UT3TXDA
HSW2_N_INT HDMI_PON O I DMI Switcher (ZONE) Interrupt (MN864807 NIRQ1)
116 PT4/INT01b/RXIN1 REM_IN2 AC I I Remote Control Pulse Input 1 (interrupt port)
117
PW7/T32A10INA1/T32A11OUTB/ISDCIN3/
T32A11INA0
WN_SPI_N_CS WN_PON O O Network CPU SPI Chip Select
118 PW6/T32A11OUTA/ISDCIN2/T32A11OUTC WN_N_RST WN_PON O O
Hardware reset (open drain) to Wireless Network
Module side
119 PW5/T32A10OUTA/ISDCIN1/T32A10OUTC WN_PON WN_PON O O NET/USB Power Supply
120
PW4/T32A11INA1/T32A10OUTB/ISDCIN0/
T32A10INA0
WN_ADT_N_
MUTE
WN_PON O O Voice Input Mute Control to Network Module Side
121
PM3/INT14b/T32A11OUTB/TSPI6CSIN/UT4CTS_
N/TSPI6CS0/UT4RTS_N
WN_DIAG WN_PON O O
DIAG control to network module side,
High: DIAG Mode
Low: Normal Mode
122
PM2/T32A11OUTA/T32A11OUTC/UT4RTS_N/
TSPI6SCK/UT4CTS_N
FPGA_SCK VID_PON O O FPGA Clock (at booting)
123 PM1/I2C3SCL/UT4TXDA/TSPI6RXD/UT4RXD DSP1_NIC DSP1_PON I I SOC
124 PM0/I2C3SDA/UT4RXD/TSPI6TXD/UT4TXDA FPGA_MOSI VID_PON O O FPGA Transmit Data (at booting)
125 PL5/INT13b/T32A08OUTB ARC_MT HDMI_PON O I eARC Mute (Sil9437)
126 PL4/INT12b/T32A08OUTA/T32A08OUTC HRT_N_INT HDMI_PON O I HDMI Repeater Interrupt (MN864807 NIRQ1)
127 DVDD3F --- --- --- --- Power Supply Port for Digital
128 DVSSF --- --- --- --- GND Port for Digital
129 PG0/INT08a/EALE/UT2RXD/UT2TXDA 232C_DBG_MOSI AC O O Debug
130 PG1/INT09a/EWAIT_N/UT2TXDA/UT2RXD 232C_DBG_MISO AC I I Debug
131
PG2/UT2RTS_N/RTC0ALARM/UT2CTS_N/
I2C0SDA
DAC1_SDA DSP2_PON O I/O DAC1, Zone2 DSP I2C Data
132 PG3/UT2CTS_N/TRGIN/UT2RTS_N/I2C0SCL DAC1_SCL DSP2_PON O O DAC1, Zone2 DSP I2C Clock
133 AINA00/PN0 AD1_COM +3.3S_PON O I AD Selector 1, COM Input
134 AINA01/PN1 AD2_COM +3.3S_PON O I AD Selector 2, COM Input
135 AINA02/PN2 PS3_PRT AC I I PS3_PRT Detection
136 AINA03/PN3 - AC O O No Use
137 AINA04/PN4 - AC O O No Use
138 AINA05/PN5 DSP1_WAKEUP DSP1_PON O O DSP1 (SOC) Wake up (also used as Audio MUTE)
139 AINA06/PN6 DSP1_PON DSP1_PON O O Input Power Control of PMIC for DSP1 (SOC)
140 AINA07/PN7 KPD_PWR_N DSP1_PON I O PMIC power trigger (Nch Open drain)
141
T32A04INB1/T32A04INC0/T32A04INA0/AINA08/
PP0
AD_SEL_A +3.3S_PON O O AD Select A
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