A
1
2
3
4
5
6
7
8
9
10
KJIHGFEDCB
L
NM
81
RX-A4A
A[10]
A_SnRAS
A_SDQ[11]
A_SCKE
HTX1_Y[8]
A_SDQ[5]
OUT1_Y[9]
A_SnCAS
A_SDQ[12]
A_SDQ[4]
OUT1_Y[1]
A_SDQ[13]
OUT1_Y[8]
HTX1_Y[1]
A_SDQ[14]
A_SDQ[2]
OUT1_C[0]
A_SDQ[15]
OUT1_DE
HTX1_Y[4]
A_SDQ[1]
HTX1_Y[3]
HTX1_C[8]
A_SDQ[7]
A_SDQ[0]
A_SDQ[6]
A_SDQ[5]
HTX1_Y[9]
A_SDQ[4]
HTX1_C[6]
A_SDQ[3]
A_SnWE
A_SDQ[2]
OUT1_HS
HTX1_DE
A_SLDQM
OUT1_VS
OUT1_Y[7]
A_SDQ[1]
HTX1_HS
OUT1_Y[5]
OUT1_CLK
A_SDQ[0]
HTX1_VS
OUT1_Y[0]
HRX_Y[0-7],HRX_C[0-7],HRX_DE,HRX_HS,HRX_VS
A_SAD[12]
HTX1_CLK
HTX1_Y[5]
HTX1_C[0]
OUT1_Y[4]
HTX1_C[1]
OUT1_C[3]
A_SUDQM
HTX1_Y[2]
HTX1_C[2]
A_SAD[8]
HTX1_C[3]
A_SAD[9]
OUT1_Y[3]
HTX1_C[4]
A_SAD[11]
A_SAD[7]
A_SDQ[15]
HTX1_Y[0]
OUT1_Y[2]
A_SAD[6]
A_SDQ[14]
HTX1_C[5]
A_SAD[5]
OUT1_C[2]
A_SDQ[13]
A_SAD[4]
A_SDQ[12]
OUT1_C[8]
A_SDQ[11]
A_SAD[3]
OUT1_Y[6]
VPO_CLK
VPO_CLK
A_SAD[2]
A_SDQ[9]
OUT1_C[4]
OUT1_C[6]
A_SDQ[8]
A_SDQ[8]
A_SAD[1]
A_SDQ[9]
A_SnCS
OUT1_C[1]
A_SDQ[7]
HTX1_Y[7]
A_SDQ[10]
HTX1_Y[6]
A_SAD[0]
OUT1_C[5]
A_SDQ[6]
HRX_G_CLK
HRX_G_CLK
FPGA_N_RD
FPGA2_N_RD
FPGA2_N_WR
A_RAMCLK
A_RAMCLK1
A_SUDQM
A_SCKE
A_SAD[9]
A_SAD[6]
A_SAD[0]
A_SAD[1]
A_SAD[4]
A_SAD[2]
A_SAD[3]
A_SnWE
A_SAD[10]
A_SAD[12]
A_SnRAS
A_SAD[13]
A_SnCAS
FPGA_N_WR
OUT1_Y[7]
OUT1_Y[8]
OUT1_Y[9]
OUT1_C[8]
OUT1_C[5]
OUT1_C[6]
OUT1_C[4]
OUT1_DE
OUT1_C[0]
OUT1_Y[5]
OUT1_Y[6]
OUT1_C[1]
OUT1_Y[3]
OUT1_CLK
OUT1_Y[4]
OUT1_Y[1]
HRX_C[5]
OUT1_Y[0]
HRX_C[4] VPO_Y[2]
HRX_HS
HRX_VS
VPO_Y[3]
HRX_C[7]
HRX_Y[6]
HRX_DE
VPO_Y[7]
HRX_Y[4]
VPO_Y[5]
HRX_Y[1]
HRX_Y[3]
HRX_Y[7]
VPO_Y[0]
VPO_Y[1]
HRX_C[1]
HRX_Y[2]
HRX_Y[5]
HRX_C[0]
HRX_C[2]
OUT1_VS
OUT1_HS
A[1]
A[3]
A[4]
A_SAD[5]
A_SAD[11]
A_SAD[7]
OUT1_C[2]
OUT1_C[3]
A_SAD[8]
A_SDQ[3]
A_SDQ[10]
A_SLDQM
A_SnCS
LOOP1
OUT1_C[7]
OUT1_C[9]
OUT1_Y[2]
A_SAD[13]
A_SAD[10]
OUT1_C[9] HTX1_C[9]
OUT1_C[7] HTX1_C[7]
A_SAD[14]
A_SAD[14]
HRX_C[6]
HRX_Y[0]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[6]
D[7]
FG_D[0]
FG_D[1]
FG_D[2]
FG_D[3]
FG_D[4]
FG_D[5]
FG_D[6]
FG_D[7]
FG_D[8]
FG_D[9]
FG_D[10]
FG_D[11]
FG_D[12]
FG_D[13]
FG_D[14]
FG_D[15]
A[5]
FG_D[0]
FG_D[3]
FG_D[4]
FG_D[5]
FG_D[6]
FG_D[7]
FG_D[8]
FG_D[9]
FG_D[10]
FG_D[11]
FG_D[12]
FG_D[15]
HRX_C[3]
VPO_C[0]
VPO_C[1]
VPO_C[2]
VPO_C[3]
VPO_C[4]
VPO_C[5]
VPO_C[6]
VPO_C[7]
VPO_C[8]
VPO_Y[4]
VPO_Y[8]
VPO_Y[9]
VPO_DE
VPO_HS
VPO_VS
FG_D[2]
FG_D[14]
FG_D[13]
VPO_Y[6]
A[6]
A[7]
VPO_C[9]
A6_V18
A7_V18
B_SDQ[6]
B_SDQ[5]
B_SDQ[3]
B_SDQ[1]
B_SDQ[8]
B_SDQ[9]
B_SDQ[10]
B_SDQ[11]
B_SDQ[12]
B_SDQ[13]
B_SDQ[14]
B_SDQ[15]
A_RAMCLK2
B_SDQ[0]
B_SDQ[2]
B_SDQ[4]
B_SDQ[7]
1_SAD[4]
1_SAD[5]
1_SAD[6]
1_SAD[7]
1_SAD[8]
1_SAD[9]
1_SAD[11]
1_SCKE
1_SAD[14]
1_SUDQM
1_SLDQM
1_SnCAS
1_SnRAS
1_SnCS
1_SAD[13]
1_SAD[12]
1_SAD[10]
1_SAD[0]
1_SAD[1]
1_SAD[2]
1_SAD[3]
A[2]A[2]
FPGA1_N_RD
FPGA1_N_RD
FPGA1_N_WR
FG_D[1]
1_SnWE
0
J513
R513
6 8
R510
6 8
R527
3 3
R512
6 8
DGND
DGND
DGND
R511
6 8
R528
no_use
DGND
R526
no_use
R529
6 8
R530
6 8
C572
10/10
C511
10/10
DGND
R533 2 2
R543
47K
HTX1_CLK,HTX1_Y[0-9],HTX1_C[0-9],HTX1_DE,HTX1_HS,HTX1_VS
R505
no_use
DGND
FPGA_N_WR
+2.5FPG1
D[0-15]
R544
2 2
+3.3DF
C542
1000P/50
IC54
EP4CE15F17C6N
E 3
VCCIO1
G 3
VCCIO1
K 3
VCCIO2
M 3
VCCIO2
P 4
VCCIO3
P 7
VCCIO3
T 1
VCCIO3
P10
VCCIO4
P13
VCCIO4
T16
VCCIO4
K14
VCCIO5
M14
VCCIO5
E14
VCCIO6
G14
VCCIO6
A16
VCCIO7
C10
VCCIO7
C13
VCCIO7
A 1
VCCIO8
C 4
VCCIO8
C 7
VCCIO8
G10
VCCINT
G 6
VCCINT
G 7
VCCINT
G 8
VCCINT
G 9
VCCINT
H1
1
VCCINT
H 6
VCCINT
K 7
VCCINT
N 4
VCCD_PLL1
D13
VCCD_PLL2
L 5
VCCA1
F12
VCCA2
B15
GND
B 2
GND
C12
GND
C 5
GND
D10
GND
D 7
GND
E13
GND
E 2
GND
E 4
GND
G13
GND
G 4
GND
H10
GND
H15
GND
H16
GND
H 7
GND
H 8
GND
H 9
GND
J10
GND
J 7
GND
J 8
GND
J 9
GND
K13
GND
K 4
GND
M13
GND
M 4
GND
N10
GND
N 7
GND
P12
GND
P 5
GND
R15
GND
R 2
GND
M 5
GNDA1
E12
GNDA2
L504
BKP1005HS680-T
+3.3DF
J507
no_use
R568
22X4
4
5 7 8
3 2 1
6
R535
2 2
R542
47K
L502
BLM21PG600SN1D
DGND
R522
1 K
+1.2FPLL
R578
22X4
1 2 4
5
3
6
DGND
DGND
R557
22X4
1 2 4
5
3
6
+2.5FPGA
L500
BKP1005HS680-T
+3.3DF
+2.5FPG1
R5381 K
R525 no_use
DGND
A[0-10]
L511
BKP1005HS680-T
+1.2FPG1
FPGA_N_RD
DGND
R520
1 K
+2.5FPGA
FPGA_MOSI
TP502
DGND
C506
10/10
R536
no_use
+3.3DF
L503
BKP1005HS680-T
R501
no_use
R576
22X4
1 2 4
5
3
67878
+1.2FPG1
DGND
DGND
R566
22X4
1 2 4
5
3
678
DGND
DGND
DGND
+1.2FPG1
FPGA_N_CFG
IC54
EP4CE15F17C6N
B16
IO6
C15
IO6
C16
IO6
D15
IO6
D16
IO6
F13
IO6
F14
IO6
F15
IO6/CLKUSR
F16
IO6/nCEO
G11
IO6
G15
IO6/CRC_ERROR
G16
IO6/INIT_DONE
A10
IO7
A11
IO7
A12
IO7
A13
IO7
A14
IO
7
A15
IO7
A 9
CLK8
B10
IO7
B11
IO7
B12
IO7
B13
IO7
B14
IO7
B 9
CLK9
C11
IO7
C14
IO7
C 9
IO7
D11
IO7
D12
IO7
D14
IO7
D 9
IO7
J11
GND
J12
IO5
J13
IO5
J14
IO5
J15
IO5/DEV_CLRn
J16
IO5/DEV_OE
K11
VCCINT
K12
IO5
K15
IO5
K16
IO5
L12
VCCA4
L13
IO5
L14
IO5
L15
IO5
L16
IO5
M12
GNDA4
N13
VCCD_PLL4
N14
IO5
N15
IO5
N16
IO5
P15
IO5
P16
IO5
R16
IO5
A 2
IO8
A 3
IO8
A 4
IO8
A 5
IO8/DATA7
A 6
IO8
A 7
IO8
A 8
CLK10
B 3
IO8
B 4
IO8
B 5
IO8
B 6
IO8
B 7
IO8/DATA4
B 8
CLK11
C 3
IO8
C 6
IO8
C 8
IO8
D 3
IO8
D 5
IO8
D 6
IO8
D 8
IO8
E 6
IO8/DATA6
E 7
IO8/DATA5
E 8
IO8/DATA2
F 6
GND
F 7
VCCINT
F 8
IO8/DATA3
F10
GND
E10
IO7
F 9
IO7
F11
VCCINT
E11
IO7
E 9
IO7
DGND
+2.5FPG1
R577
22X4
+1.2PLL1
VID_PON
R517
10K
R574
22X4
4
5 7 8
3 2 12 1
6
R539
10K
IC54
EP4CE15F17C6N
J 1
IO2
J 2
IO2
J 6
VCCINT
K 1
IO2
K 2
IO2
K 5
IO2
K 6
IO2
L 1
IO2
L 2
IO2
L 3
IO2
L 4
IO2
L 6
IO2
N 1
IO2
N 2
IO2
P 1
IO2
P 2
IO2
R 1
IO2
K 8
GND
L 7
IO3
L 8
IO3
M
6
IO3
M 7
IO3
M 8
IO3
N 3
IO3
N 5
IO3
N 6
IO3
N 8
IO3
P 3
IO3
P 6
IO3
P 8
IO3
R 3
IO3
R 4
IO3
B 1
IO1
C 2
IO1
D 1
IO1
D 4
VCCD_PLL3
E 5
GNDA3
F 1
IO1
F 2
IO1
F 3
IO1
F 5
VCCA3
G 1
IO1
G 2
IO1
G 5
IO1
K10
IO4
K 9
IO4
L10
IO4
L11
IO4
L 9
IO4
M10
IO4
M11
IO4
M 9
IO4
N11
IO4
N12
IO4
N 9
IO4
P11
IO4
P14
IO4
P 9
IO4
R10
IO4
R11
IO4
R12
IO4
R13
IO4
R14
IO4
R 9
CLK13
T10
IO4
T11
IO4
T12
IO4
T13
IO4
T14
IO4
T15
IO4
T 9
CLK12
R 8
CLK15
R 5
IO3
T 5
IO3
T 4
IO3
T 8
CLK14
T 3
IO3
T 2
IO3
T 6
IO3
R 6
IO3
T 7
IO3
R 7
IO3
DGND
FPGA_SCK
C550
10/10
R565
22X4
4
5 7 8
3 2 1
6
+3.3FPG1
DGND
R521
1 K
DGND
+1.2FP1
+2.5FPG1
R531
1 K
+2.5FPG1
R532
2 2
DGND
R514
10K
J502
no_use
0
J509
C500
1000P/50
+1.2FPG1
R560
22X4
1 2 4
5
3
6
+3.3FPG1
R567
22X4
R553
2 2
R564
22X4
R556
22X4
1 2 4
5
3
678 78
+1.2PLL1
R555
2 2
J506
no_use
DGND
C531
10/10
+3.3FPG1
DGND
+1.2FPLL
DGND
0
J505
R523 no_use
R554
2 2
TP501
+1.2PLL1
L505
BKP1005HS680-T
FPGA_N_CS
DGND
DGND
DGND
+1.2FPG
1
0
J508
DGND
R515
10K
DGND
IC54
EP4CE15F17C6N
H13
MSEL0
H12
MSEL1
G12
MSEL2
H 5
nCONFIG
F 4
nSTATUS
J 3
nCE
H14
CONF_DONE
H 1
DCLK
H 2
IO1/DATA0
C 1
IO1/DATA1/ASDO
D 2
IO1/FLASH_nCE/nCSO
H 3
TCK
H 4
TDI
J 4
TDO
J 5
TMS
E 1
CLK1
M 2
CLK2
M 1
CLK3
E15
CLK4
E16
CLK5
M15
CLK6
M16
CLK7
R575
22X4
4
5 7 8
3
6
R540
10K
DGND
DGND
+3.3FPG1
R516
10K
DGND
R524 no_use
R561
22X4
1 2 4
5
3
6
R503
6 8
+3.3HDV
FPGA2_N_CS
VPO_CLK,VPO_C[0-9],VPO_Y[0-9],VPO_HS,VPO_VS,VPO_DE
HRX_Y[0-7],HRX_C[0-7],HRX_DE,HRX_HS,HRX_VS
HRX_G_CLK
FPGA2_N_RD
FPGA2_N_WR
R545
no_use
DGND
R550
2 2
R551
2 2
TP508
TP509
+3.3DF
L512
BKP1005HS680-T
R541
47K
C504
1000P/50
R506
1 K
R502
1 K
R534
2 2
R570
0X4
4
5 7 8
3 2 1
6
R573
0X4
1 2 4
5
3
6
R571
0X4
1 2 4
5
3
6
R569
0X4
1 2 4
5
3
6
L506
BLM21PG600SN1D
C557
1/25
R518
0
C561
no_use
+3.3DF +3.3DV
C562
1/25
0
J510 J511
no_use
J503
no_use
0
J504
FPGA_PON
TP506
D 5 0 1
no_use
D 5 0 0
no_use
D 5 0 2
no_use
D 5 0 3
no_use
W9825G6KH-6 X4943E0IC59
1
VDD
2
DQ0
3
VDDQ
4
DQ1
5
DQ2
6
VSSQ
7
DQ3
8
DQ4
9
VDDQ
1 0
DQ5
1 1
DQ6
1 2
VSSQ
1 3
DQ7
1 4
VDD
1 5
LDQM
1 6
W E
1 7
CAS
1 8
RAS
1 9
C S
2 0
BS0
2 1
BS1
2 2
A10/AP
2 3
A 0
2 4
A 1
2 5
A 2
2 6
A 3
2 7
VDD
2 8
VSS
2 9
A 4
3 0
A 5
3 1
A 6
3 2
A 7
3 3
A 8
3 4
A 9
3 5
A11
3 6
A12
3 7
CKE
3 8
CLK
3 9
UDQM
4 0
N C
4 1
VSS
4 2
DQ8
4 3
VDDQ
4 4
DQ9
4 5
DQ10
4 6
VSSQ
4 7
DQ11
4 8
DQ12
4 9
VDDQ
5 0
DQ13
5 1
DQ14
5 2
VSSQ
5 3
DQ15
5 4
VSS
IC57
R5527K001D-TR
1
Vin
2
GND
4
Vout
3
O n
G
IC52
TC7SZ125FU
5
3
IC52
2 4
1
IC56
V +
1 4
IC56
V -
7
74LCX32FT
IC56
9
1 0
8
IC56
1 2
1 3
1 1
IC56
74LCX32FT
1
2
3
IC56
4
5
6
C543
1/25
C554
1/25
C555
1/25
C556
1/25
IC61
TC7SZ04FU
2 4
IC61
5
VCC
3
GND
1
N C
DGND
CB50
no_use
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
+1.8FPG1
R500
1 K
C502
1000P/50
C516
10/10
L501
BKP1005HS680-T
TP500
DGND
DGND
TP511
0
J500
+1.8FPG1
A6_V18
A7_V18
XL50
27.000MHZ
ZX29870
1
O E
2
GND
3
OUTPUT
4
VCC
C593
1000P/50
DGND
L513
BLM15PD600SN1D
R537
100
C591
1000P/50
DGND
+3.3DF
DGND
FPGA2_27MHZ
IC64
V -
7
IC64
74LCX126FT
1 2 11
5 6
IC64
V +
1 4
2 3
DGND
9 8
DGND
+3.3DF
R579
100
R580
100
C603
1000P/50
FPGA_PON
IC51
TLV74112PDQN
R
I N
E N
OUT
GND
G
IC50
TLV74118PDQNR
I N
E N
OUT
GND
G
IC55
TLV74125PDQNR
I N
E N
OUT
GND
G
C510
1/25
R581
no_use
DGND
C509
1/25
+3.3DF
TP513
IC53
RP508K121B-TR
1
VOUT
2
MODE
3
C E
L X
5
4
VIN
6
GND
L509
BLM21PG600SN1D
DGND
R507
10K
0
J501
L507
BLM21PG600SN1D
L508
1UH
DGND
R508
no_use
+3.3DF
+1.2FP1
DGND
R504
1 K
TP523
TP524
TP525
TP526
TP528
TP527
TP529
TP530
TP520
TP518
TP521
TP519
TP522
TP515
TP516
TP517
TP514
TP531
TP532
TP535
TP534
TP533
TP536
TP537
TP538
TP540
TP539
TP541
C571
C570
C560
10P/50
C569
VFP_PON
DGND
C553
0.1/16
C548
0.1/16
DGND
C558
0.1/16
C549
0.1/16
+3.3DF
C559
0.1/16
R509
1 0
R519
1 0
R558
1 0
TP510
C539
0.1/16
C530
0.1/16
C599
0.1/16
C573
0.1/16
C574
0.1/16
C575
0.1/16
C525
0.1/16
C602
0.1/16
C589
0.1/16
C518
0.1/16
C526
0.1/16
C590
0.1/16
C598
0.1/16
C596
0.1/16
C508
0.1/16
C537
0.1/16
C517
0.1/16
C519
0.1/16 C513
0.1/16
C594
0.1/16
C515
0.1/16
C545
0.1/16
C529
0.1/16
C523
0.1/16
C533
0.1/16
C534
0.1/16
C551
0.1/16
C577
0.1/16
C597
0.1/16
C520
0.1/16
C600
0.1/16
C527
0.1/16
C514
0.1/16
C546
0.1/16
C528
0.1/16
C547
0.1/16
C579
0.1/16
C535
0.1/16
C552
0.1/16
C521
0.1/16
C524
0.1/16
C595
0.1/16
C592
0.1/16
C536
0.1/16
C538
0.1/1
6
C576
0.1/16
C532
0.1/16
C522
0.1/16
C578
0.1/16
C540
0.1/16
C512
0.1/16
C601
0.1/16
C544
0.1/16
TP507
TP543
TP542
TP545
TP546
TP547
TP548
TP549
TP544
TP557
TP558
TP559
TP560
TP561
TP562
TP563
TP564
TP565
C503
47/6.3(B)
C501
47/6.3(B)
C505
47/6.3(B)
C507
4.7/25
C541
4.7/25
TP555
TP552
TP554
655PT355PT
TP550
R552
2 2
R546
1 K
R549
1 K
R547
1.2K
R548
1.2K
S h e e t4: F P GA( G U I )
IC/CB/XL:50-79
OTHER :500-799
FPGA_N_CS
FPGA2_N_CS
FPGA1_N_CS
FPGA_SCL
FPGA_N_CFG
DATA
CONF_DONE
DCLK
N_CS
ASDI
N_CONFIG
N_STATUS
to 006.sht
(u-Com)
to 002.sht
(HDMI 807)
to 002.sht
(HDMI 807)
MSEL1
FPGA_MOSI
DGND
DGND
N_STATUS
N_CE
+3.3V
N_CS
DGND
FPGA_CDONE
ASDI
to 006.sht
(u-Com)
DATA
Standard
PS AS
MSEL0 0 0
MSEL1 0 1
MSEL2 0 0
MSEL3 0 0
CONF_DONE
N_CONFIG
DCLK
N_CE
FPGA_N_STA
LOOP1
LOOP1
FPGA1_N_CS
FPGA1_N_WR
to 005.sht
(FPGA VP)
From 003/005.sht
(VDEC/FPGA VP)
IC 5 4
IC54
25 6 M WIN B O N D : X 4 943E 0 W 982 5 G 6KH - 6
Ze n t el : Y F 9 6 1B0 A 3 V56 S 4 0GT P - 6 0
A8A,A6A only
MODE
Bank1-4:3.3V
Bank5-8:1.8V
3.3V -> 1.8V
A8/B9/M16
B9/A8 : 3.3->1.8V
R548,R549
A
R546,R547
A
R523,R524,R525
A
J506,J507
A
J508,J509
A
J502
A
J503,J504
A
TP500,TP501,TP502,TP513,TP506
B
A8A,A6A only
7878
78 78 78
Pin No.
1
2
3
4
5
Symbol
V
OUT
6 GND
CE
Description
Output Pin
V
IN
Input Pin
L
x
LX Switching Pin
Ground Pin
MODE
Mode Control Pin
(“H” forced PWM control,
“L” PWM/VFM auto switching control)
Chip Enable Pin ("H" Active)
IC53: RP508K121B-TR
Voltage regulator
CE
V
IN
GND
L
X
Chip
Enable
Current
Detecto
Switching
Control
UVLO
OSC
Vref
V
OUT
Mode
Control
Soft Start
MODE
Thermal
Protection
RIPPLE
Control
Delay
Control
+
Delay
Clock
Gene
ator
1
5
4
2
3
6
DQ0
DQ15
LDQM
UDQM
CLK
CKE
CS
RAS
CAS
WE
A10
A0
A9
A11
A12
BS0
BS1
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
Note: The cell array configuration is 8192 * 512 * 16.
ROW DECODER
ROW DECODER
ROW DECODERROW DECODER
IC59: W9825G6KH-6
High-speed synchronous dynamic random access memory (SDRAM)
IC57: R5527K001D-TR
Pin No.
1
2
3
4
Symbol
GND
ON
V
OUT
VIN
Description
Ground Pin
ON/OFF Control Pin, Active High/Low
Switch Output Pin
Supply Input Pin
3A Load switch IC
V
Reverse
Detector
Soft
Start
Charge
Pump
4
V
OUT
2
GND
IN
ON
1
3
Current
Limit
UVLO
Bandgap
IN
EN
OUT
Logic
GND
TLV741P
120
Thermal
Shutdown
IC51: TLV74112PDQNR
IC55: TLV74125PDQNR
IC50: TLV74118PDQNR
Low-Dropout Regulator With Foldback Current Limit
IC52: TC7SZ125FU
Bus buffer 3-state output
5
4
Vcc
OUT Y
1
3
2
GND
IN A
G
IC56: 74LCX32FT
Low-Voltage Quad 2-Input OR Gate
with 5-V Tolerant Inputs and Outputs
FPGA GUI
SDRAM
to DIGITAL 2/8
to DIGITAL 3/8
to DIGITAL 5/8
to DIGITAL 4/8
to DIGITAL 4/8
to DIGITAL 2/8
DIGITAL
REMARKS
CAPACITOR
PARTS NAME
NO
NO
MARK
MARK
ELECTROLYTIC CAPAC I T O R
CERAMIC CAPACI T O R
POLYESTER FILM CA P A CIT O R
POLYSTYRENE FILM C A P A C I TOR
MICA CAPACITOR
POLYPROPYLENE F I L M CAPACITOR
SEMICONDUCTIVE CERAMI C CAPACITOR
P
SOLID ELECTROLYTIC CAPAC ITOR
TUBULAR CAPACITORCERAMIC
NOTICE
U.S.A
G
CANADA
EUROPEAN STANDARD
L
CHINA
AUSTRALIA
SINGAPORE
KOREA
GENERAL
U
C
T
A
K
R
JAPAN
(model)
B BRITISH
J
SOUTH EUROPEE
V TAIWAN
F RUSSIAN
P LATIN AMERIC A
S BRAZIL
H THAI
RESISTOR
REMARKS
NO MARK
PARTS NAME
CARBON
CARBON
METAL
METAL
METAL
FIRE
CEMENT
SEMI
FILM RESIS TOR
FILM RESIS TOR
OXIDE FILM RESISTOR
FILM RE SISTOR
PLATE RESISTOR
PROOF CARBON FILM RESISTO R
MOLDED RESI STOR
VARIABLE R E S I STOR
(P=5)
(P=10)
CHIP RESIST O R
+3.28V
+1.19V
+2.50V
+1.20V
+1.80V
No replacement
part available.
サービス部品供給なし
No replacement
part available.
サービス部品供給なし
No replacement
part available.
サービス部品供給なし
No replacement
part available.
サービス部品供給なし
No replacement
part available.
サービス部品供給なし
No replacement
part available.
サービス部品供給なし
DIGITAL 3/8
Details of colored lines
Red / full line: Power supply (+)
Red /dashed line: Power supply (-)
Orange: Signal detect
Yellow: Clock
Green: Protection detect
Brown: Reset signal
Blue: Panel key input
★ All voltages are measured with a 10 MΩ/V DC electronic
voltmeter.
★ Components having special characteristics are marked ⚠
and must be replaced with parts having specifications equal
to those originally installed.
★ Circuit diagram is subject to change without notice.
● 電圧は、内部抵抗 10 MΩ の電圧計で測定したものです。
● ⚠印のある部品は、安全性確保部品を示しています。部品
の交換が必要な場合、パーツリストに記載されている部品
を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更する
ことがあります。
To Next Page