ABB REG650 - Logic Diagram

12.3.4.4 Logic diagram
QA1_OP
QB1_OP
QA1_CL
QB1_CL
QB2_CL
QB2_OP
QC3_OP
QC4_CL
S2QC2_CL
QC4_OP
S2QC2_OP
S1QC1_CL
S1QC1_OP
1
QA1OPITL
QA1OPREL
en04000542.vsd
=1
=1
=1
=1
=1
=1
=1
QC3_CL
VPS2QC2
VPS1QC1
VPQC4
VPQC3
VPQB2
VPQB1
VPQA1
A1A2_BS
&
>1
&
&
VPQB1
QB1_OP
QA1O_EX1
VPQB2
QB2_OP
QA1O_EX2
VP_BBTR
BBTR_OP
EXDU_12
QA1O_EX3
1
QA1CLITL
&
QA1CLRELVPQB1
VPQB2
&
>1
&
1
QB1ITL
QB1REL
VPQA1
VPQC3
VPQC4
VPS1QC1
QA1_OP
QC3_OP
QC4_OP
S1QC1_OP
VPQC3
VPS1QC1
QC3_CL
S1QC1_CL
EXDU_ES
EXDU_ES
QB1_EX1
QB1_EX2
IEC04000542 V1 EN
Section 12 1MRK 502 048-UEN A
Control
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