ABB REG650 - Configurable Logic Blocks; Standard Configurable Logic Blocks; Functionality

PulseTime
Ondelay
Output 1
PulseTime
Ondelay
Output 2
PulseTime
Ondelay
Output 3
Input 17
I
n
p u
t 3
2
Input 1
I n p u t 1
6
IEC09000612_2_en.vsd
³1
³1
³1
³1
&
&
&
&
&
&
ModeOutput1=Pulsed
³1
ModeOutput2=Pulsed
³1
ModeOutput3=Pulsed
t
t
t
Offdelay
t
t
t
t
Offdelay
t
Offdelay
t
IEC09000612 V2 EN
Figure 216: Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order to
obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.
13.3 Configurable logic blocks
13.3.1 Standard configurable logic blocks
13.3.1.1 Functionality
A number of logic blocks and timers are available for the user to adapt the
configuration to the specific application needs.
• OR function block. Each block has 6 inputs and two outputs where one is
inverted.
• INVERTER function blocks that inverts the input signal.
1MRK 502 048-UEN A Section 13
Logic
439
Technical manual