Abov A96G174 - Page 97

A96G174/A96S174 User’s manual 11. Timer 0/1/2
97
T1DDRH (Timer 1 D Data High Register): DCH
7
6
5
4
3
2
1
0
T1DDRH7
T1DDRH6
T1DDRH5
T1DDRH4
T1DDRH3
T1DDRH2
T1DDRH1
T1DDRH0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1DDRH[7:0]
T1 D Data High Byte
T1DDRL (Timer 1 D Data Low Register): DBH
7
6
5
4
3
2
1
0
T1DDRL7
T1DDRL6
T1DDRL5
T1DDRL4
T1DDRL3
T1DDRL2
T1DDRL1
T1DDRL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
T1DDRL[7:0]
T1 D Data Low Byte
T1CRH (Timer 1ControlHigh Register): BBH
7
6
5
4
3
2
1
0
T1EN
T1BEN
T1MS1
T1MS0
–
–
T1PE
T1CC
R/W
R/W
R/W
R/W
–
–
R/W
R/W
Initial value: 00H
T1EN
Control Timer 1
0
Timer 1 disable
1
Timer 1 enable (Counter clear and start)
T1EN
Control Complementary PWM
0
Complementary PWM disable
1
Complementary PWM enable
T1MS[1:0]
Control Timer 1 Operation Mode
T1MS1
T1MS0
Description
0
0
Timer/counter mode (T1O: toggle at A match)
0
1
Capture mode (The A match interrupt can occur)
1
0
PPG one-shot mode (PWM1O)
1
1
PPG repeat mode (PWM1O)
T1PE
Control Timer 1 port output
0
Timer 1 output disable
1
Timer 1 output enable
T1CC
Clear Timer 1 Counter
0
No effect
1
Clear the Timer 1 counter (When write, automatically
cleared “0” after being cleared counter)