Publication 1763-RM001C-EN-P - October 2009
Using the High-Speed Counter and Programmable Limit Switch 103
The UFM (Underflow Mask) control bit is used to enable (allow) or
disable (not allow) a underflow interrupt from occurring. If this bit is clear
(0), and a Underflow Reached condition is detected by the HSC, the HSC
user interrupt is not executed.
This bit is controlled by the user program and retains its value through a
power cycle. It is up to the user program to set and clear this bit.
Underflow Interrupt (UFI)
The UFI (Underflow Interrupt) status bit is set (1) when the HSC
accumulator counts through the underflow value and the HSC interrupt is
triggered. This bit can be used in the control program to identify that the
underflow condition caused the HSC interrupt. If the control program
needs to perform any specific control action based on the underflow, this
bit is used as conditional logic.
This bit can be cleared (0) by the control program and is also cleared by
the HSC sub-system whenever these conditions are detected:
• Low Preset Interrupt executes
• High Preset Interrupt executes
• Overflow Interrupt executes
• Controller enters an executing mode
Overflow (OF)
The OF (Overflow) status flag is set (1) by the HSC sub-system whenever
the accumulated value (HSC:0.ACC) has counted through the overflow
variable (HSC:0.OF).
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 107.
Type User Program Access
UFI - Underflow
Interrupt
HSC:0/UFI bit 2 to 7 status read/write
Description Address Data Format
HSC Modes
(1)
(1) For Mode descriptions, see HSC Mode (MOD) on page 107.
Type User Program Access
OF - Overflow HSC:0/OF bit 0 to 7 status read/write
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