Publication 1763-RM001C-EN-P - October 2009
Conversion Instructions 205
Updates to Math Status Bits
The two rungs shown cause the controller to verify that the value I:0
remains the same for two consecutive scans before it executes the FRD.
This prevents the FRD from converting a non-BCD value during an input
value change.
Example
The BCD value 32,760 in the math register is converted and stored in
N7:0. The maximum source value is 32767 (BCD).
Math Status Bits
With this Bit: The Controller:
S:0/0 Carry always resets
S:0/1 Overflow sets if non-BCD value is contained at the source or the value to be
converted is greater than 32,767; otherwise resets. On overflow,
the minor error flag is also set.
S:0/2 Zero Bit sets if result is zero, otherwise resets
S:0/3 Sign Bit always resets
TIP
Always provide ladder logic filtering of all BCD input
devices prior to performing the FRD instruction. The
slightest difference in point-to-point input filter delay can
cause the FRD instruction to overflow due to the
conversion of a non-BCD digit.
TIP
To convert numbers larger than 9999 BCD, the source
must be the Math Register (S:13). You must reset the
Minor Error Bit (S:5.0) to prevent an error.
]/[
S:1
15
EQU
EQUAL
Source A N7:1
0
Source B I:0.0
0
MOV
MOVE
Source I:0.0
0
Dest N7:1
0
FRD
FROM BCD
Source I:0.0
0
Dest N7:2
0
efesotomasyon.com - Allen Bradley,Rockwell,plc,servo,drive
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