Atmel ATtiny26 User Manual

17
ATtiny26(L)
1477G–AVR–03/05
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement
mode features a 63 address locations reach from the base address given by the Y- or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of inter-
nal data SRAM in the ATtiny26(L) are all accessible through all these addressing
modes.
See “Program and Data Addressing Modes” on page 10 for a detailed description of the
different addressing modes.
EEPROM Data Memory The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written (see “Memory
Programming” on page 107). The EEPROM has an endurance of at least 100,000
write/erase cycles per location.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.
The write access time is typically 8.3 ms. A self-timing function lets the user software
detect when the next byte can be written. A special EEPROM Ready Interrupt can be
set to trigger when the EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed.
EEPROM Address Register –
EEAR
• Bit 7 – RES: Reserved Bits
This bit are reserved bit in the ATtiny26(L) and will always read as zero.
• Bit 6..0 – EEAR6..0: EEPROM Address
The EEPROM Address Register – EEAR – specifies the EEPROM address in the 128
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
127. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Bit 76543210
$1E ($3E) – EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEAR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value0XXXXXXX

Atmel ATtiny26 Specifications

General

Brand	Atmel
Model	ATtiny26
Category	Microcontrollers
Language	English

Summary

Features

High-performance, Low-power AVR0 8-bit Microcontroller

High-performance, low-power 8-bit AVR microcontroller with RISC architecture.

RISC Architecture

Describes the RISC architecture of the ATtiny26(L) microcontroller.

Data and Non-volatile Program Memory

Details the Flash, EEPROM, and SRAM memory specifications.

Peripheral Features

Lists peripheral features like Timers, ADC, Comparator.

Special Microcontroller Features

Highlights features like low power modes, reset, interrupts.

Operating Voltages

Defines the operating voltage ranges for ATtiny26L and ATtiny26.

Speed Grades

Specifies the operating speed ranges for ATtiny26L and ATtiny26.

Power Consumption

Details power consumption in active and idle modes.

Pin Configuration

Description

Block Diagram

Pin Descriptions

Port A (PA7..PA0)

Describes Port A as an 8-bit general purpose I/O port with alternate functions.

Port B (PB7..PB0)

Describes Port B as an 8-bit general purpose I/O port with alternate functions.

AVR CPU Core

Architectural Overview

Explains the AVR RISC architecture and register file concept.

Status Register 0 SREG

Stack Pointer 0 SP

Program and Data Addressing Modes

Register Direct, Two Registers Rd and Rr

Details direct register addressing for two registers.

I/O Direct

Explains direct addressing for I/O memory locations.

Data Indirect with Displacement

Describes indirect addressing with displacement calculation.

Data Indirect with Pre-decrement

Explains indirect addressing with pre-decrement operation.

Data Indirect with Post-increment

Details indirect addressing with post-increment operation.

Indirect Program Addressing, IJMP and ICALL

Covers indirect addressing for program memory jumps and calls.

Memories

In-System Programmable Flash Program Memory

Details the 2K byte in-system programmable Flash memory for program storage.

SRAM Data Memory

Describes the 128 bytes of internal SRAM organization and usage.

EEPROM Data Memory

Covers the 128 bytes of EEPROM memory, organization, and read/write access.

System Clock and Clock Options

Clock Sources

Lists selectable clock source options via Flash Fuse bits.

Crystal Oscillator

External RC Oscillator

Calibrated Internal RC Oscillator

External Clock

High Frequency PLL Clock 0 PLLCLK

System Control and Reset

Power-on Reset

Details the on-chip detection circuit for power-on reset generation.

External Reset

Explains how to generate an external reset via the RESET pin.

Brown-out Detection

Describes the on-chip BOD circuit for monitoring VCC level during operation.

Power Management and Sleep Modes

MCU Control Register 0 MCUCR

Contains control bits for general MCU functions, including sleep modes.

Idle Mode

Stops CPU, allows peripherals to run; halts clkCPU and clkFLASH.

ADC Noise Reduction Mode

Halts clkIO, clkCPU, clkFLASH; improves ADC noise environment.

Power-down Mode

Stops external oscillator; halts most clocks, allows async modules to run.

Standby Mode

Similar to power-down, but keeps the oscillator running.

I/O Ports

Ports as General Digital I/O

Describes bi-directional I/O ports with optional internal pull-ups.

Alternate Port Functions

Details alternate functions for port pins beyond general digital I/O.

Interrupts

Interrupt Vectors

Lists interrupt sources, program vectors, and priority levels.

Interrupt Handling

Explains interrupt occurrence, disabling, and response time.

External Interrupt

Pin Change Interrupt

Timer/Counters

8-bit Timer/Counter0

Details the 8-bit Timer/Counter0, its block diagram, and control registers.

8-bit Timer/Counter1

Covers Timer/Counter1 modes, prescalers, and PWM capabilities.

Watchdog Timer

Universal Serial Interface 0 USI

Register Descriptions

Describes USI data register, status register, and control register.

Functional Descriptions

Explains three-wire and two-wire modes, and alternative USI usages.

Analog Comparator

Analog to Digital Converter

Features

Lists key features of the 10-bit successive approximation ADC.

ADC Conversion Result

Explains how to find and interpret the ADC conversion result.

Memory Programming

Program and Data Memory Lock Bits

Details lock bits for protecting Flash and EEPROM programming.

Fuse Bits

Signature Bytes

Calibration Byte

Page Size

Parallel Programming Parameters, Pin Mapping, and Commands

Parallel Programming

Describes the algorithm to put the device into parallel programming mode.

Serial Downloading

Explains programming via the serial SPI bus interface.

Electrical Characteristics

Absolute Maximum Ratings*

Lists the stress limits beyond which damage may occur to the device.

DC Characteristics

Provides DC electrical parameters like voltage thresholds and currents.

ADC Characteristics

Details ADC performance metrics for single-ended and differential channels.

ATtiny26 Typical Characteristics

Register Summary

Instruction Set Summary

Ordering Information

Packaging Information

20P3

Details the 20-lead PDIP package dimensions and specifications.

20S

Details the 20-lead SOIC package dimensions and specifications.

32M1-A

Details the 32-pad MLF package dimensions and specifications.

Errata

Datasheet Revision History