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ATtiny26(L)

1477G–AVR–03/05

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used, the corresponding setup must be performed in the actual Data Direction Control

Timer/Counter0 – TCNT0

The Timer/Counter0 is implemented as an up-counter with read and write access. If the

Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues

counting in the timer clock cycle following the write operation.

8-bit Timer/Counter1 The Timer/Counter1 has two clocking modes: a synchronous mode and an asynchro-

nous mode. The synchronous mode uses the system clock (CK) as the clock timebase

and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base.

The PCKE bit from the PLLCSR Register enables the asynchronous mode when it is set

(“1”). The Timer/Counter1 general operation is described in the asynchronous mode and

the operation in the synchronous mode is mentioned only if there is differences between

these two modes. Figure 39 shows Timer/Counter1 synchronization register block dia-

gram and synchronization delays in between registers. Note that all clock gating details

are not shown in the figure. The Timer/Counter1 Register values go through the internal

synchronization registers, which cause the input synchronization delay, before affecting

the counter operation. The registers TCCR1A, TCCR1B, OCR1A, OCR1B, and OCR1C

can be read back right after writing the register. The read back values are delayed for

the Timer/Counter1 (TCNT1) Register and flags (OCF1A, OCF1B, and TOV1), because

of the input and output synchronization.

This module features a high resolution and a high accuracy usage with the lower pres-

caling opportunities. Timer/Counter1 can also support two accurate, high speed, 8-bit

Pulse Width Modulators using clock speeds up to 64 MHz. In this mode, Timer/Counter1

and the Output Compare Registers serve as dual stand-alone PWMs with non-overlap-

ping non-inverted and inverted outputs. Refer to page 74 for a detailed description on

this function. Similarly, the high prescaling opportunities make this unit useful for lower

speed functions or exact timing functions with infrequent actions.

Bit 76543210

$32 ($52) MSB LSB TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Atmel ATtiny26 User Manual

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