35
ATtiny26(L)
1477G–AVR–03/05
MCU Status Register –
MCUSR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set (one) if a Watchdog Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set (one) if a Brown-out Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set (one) if an External Reset occurs. The bit is reset (zero) by a Power-on
Reset, or by writing a logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set (one) if a Power-on Reset occurs. The bit is reset (zero) by writing a logic
zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and
then reset (zero) the MCUSR as early as possible in the program. If the register is
cleared before another reset occurs, the source of the reset can be found by examining
the reset flags.
Bit 76543210
$34 ($54) ––––WDRFBORFEXTRFPORFMCUSR
Read/Write R R R R R/W R/W R/W R/W
Initial Value0000 See Bit Description
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