121
ATtiny26(L)
1477G–AVR–03/05
Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET
is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 59 on page 121, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface. Note that throughout the descrip-
tion about Serial downloading, MOSI and MISO are used to describe the serial data in
and serial data out respectively.
Serial Programming Pin
Mapping
Figure 67. Serial Programming and Verify
(1)
Notes: 1. If the device is clocked by the internal oscillator, there is no need to connect a clock
source to the XTAL1 pin.
2. V
CC
-0.3V < AVCC < V
CC
+0.3V, however, AVCC should always be within 2.7 - 5.5V.
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
High: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
≥ 12 MHz
Table 59. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB0 I Serial data in
MISO PB1 O Serial data out
SCK PB2 I Serial clock
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
PB0
PB1
PB2
2.7 - 5.5V
AVCC
2.7 - 5.5V
(2)
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