57
ATtiny26(L)
1477G–AVR–03/05
Interrupts
Interrupt Vectors The ATtiny26(L) provides eleven interrupt sources. These interrupts and the separate
Reset Vector, each have a separate program vector in the program memory space. All
the interrupts are assigned individual enable bits which must be set (one) together with
the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 29. The list
also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the Exter-
nal Interrupt Request 0 etc.
The most typical and general program setup for the Reset and Interrupt Vector
Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset handler
$001 rjmp EXT_INT0 ; IRQ0 handler
$002 rjmp PIN_CHANGE ; Pin change handler
$003 rjmp TIM1_CMP1A ; Timer1 compare match 1A
$004 rjmp TIM1_CMP1B ; Timer1 compare match 1B
$005 rjmp TIM1_OVF ; Timer1 overflow handler
$006 rjmp TIM0_OVF ; Timer0 overflow handler
$007 rjmp USI_STRT ; USI Start handler
$008 rjmp USI_OVF ; USI Overflow handler
$009 rjmp EE_RDY ; EEPROM Ready handler
$00A rjmp ANA_COMP ; Analog Comparator handler
$00B rjmp ADC ; ADC Conversion Handler
;
$009 RESET: ldi r16, RAMEND ; Main program start
$00A out SP, r16
Table 29. Reset and Interrupt Vectors
Vector No Program Address Source Interrupt Definition
1 $000 RESET Hardware Pin and Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 I/O Pins Pin Change Interrupt
4 $003 TIMER1, CMPA Timer/Counter1 Compare Match 1A
5 $004 TIMER1, CMPB Timer/Counter1 Compare Match 1B
6 $005 TIMER1, OVF1 Timer/Counter1 Overflow
7 $006 TIMER0, OVF0 Timer/Counter0 Overflow
8 $007 USI_STRT USI Start
9 $008 USI_OVF USI Overflow
A $009 EE_RDY EEPROM Ready
B $00A ANA_COMP Analog Comparator
C $00B ADC ADC Conversion Complete
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