Atmel ATtiny26

33
ATtiny26(L)
1477G–AVR–03/05
Figure 26. MCU Start-up, RESET Tied to VCC
Figure 27. MCU Start-up, RESET
Controlled Externally
External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer
than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage – V
RST
– on its positive edge, the delay timer starts the MCU after the Time-out
period t
TOUT
has expired.
Figure 28. External Reset During Operation
VCC
RESET
T
IME-OUT
I
NTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
RESET
T
IME-OUT
I
NTERNAL
RESET
t
TOUT
V
POT
V
RST
VCC
RESET
T
IME-OUT
I
NTERNAL
RESET
t
TOUT
V
RST