Atmel ATtiny26

4
ATtiny26(L)
1477G–AVR–03/05
Block Diagram Figure 1. The ATtiny26(L) Block Diagram
WATCHDOG
TIMER
MCU CONTROL
REGISTER
UNIVERSAL
SERIAL
INTERFACE
TIMER/
COUNTER0
DATA DIR.
REG.PORT A
DATA REGISTER
PORT A
PROGRAMMING
LOGIC
TIMING AND
CONTROL
TIMER/
COUNTER1
MCU STATUS
REGISTER
PORT A DRIVERS
PA0-PA7
VCC
GND
+
-
ANALOG
COMPARATOR
8-BIT DATA BUS
ADC
ISP INTERFACE
INTERRUPT
UNIT
EEPROM
INTERNAL
OSCILLATOR
OSCILLATORS
CALIBRATED
OSCILLATOR
INTERNAL
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PORT B DRIVERS
PB0-PB7
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
STATUS
REGISTER
Z
Y
X
ALU
CONTROL
LINES
AVCC