85
ATtiny26(L)
1477G–AVR–03/05
Functional Descriptions
Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0
and 1, but does not have the slave select (SS) pin functionality. However, this feature
can be implemented in software if necessary. Pin names used by this mode are: DI, DO,
and SCK.
Figure 45. Three-wire Mode Operation, Simplified Diagram
Figure 45 shows two USI units operating in Three-wire mode, one as master and one as
slave. The two shift Registers are interconnected in such way that after eight SCK
clocks, the data in each register are interchanged. The same clock also increments the
USI’s 4-bit counter. The Counter Overflow (interrupt) flag, or USIOIF, can therefore be
used to determine when a transfer is completed. The clock is generated by the master
device software by toggling the PB2 pin via the PORTB Register or by writing a one to
the USITC bit in USICR.
Figure 46. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in Figure 46. At the top of the figure is a SCK
cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these
cycles. The SCK timing is shown for both external clock modes. In external clock mode
0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (Data Register is
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBy
PBx
PBz
DO
DI
SCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PBy
PBx
PBz
DO
DI
SCK
PORTBz
MSB
MSB
654321LSB
1 2 3 4 5 6 7 8
654321LSB
SCK
SCK
DO
DI
DCBA E
CYCLE
( Reference )
To Next Page
Loading...
Need help?
General
