21
ATtiny26(L)
1477G–AVR–03/05
Note: 1. Reserved and unused locations are not shown in the table.
All ATtiny26(L) I/O and peripheral registers are placed in the I/O space. The I/O loca-
tions are accessed by the IN and OUT instructions transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address
range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instruc-
tions. Refer to the instruction set chapter for more details. For compatibility with future
devices, reserved bits should be written zero if accessed. Reserved I/O memory
addresses should never be written.
$06($26) ADCSR ADC Control and Status Register
$05($25) ADCH ADC Data Register High
$04($24) ADCL ADC Data Register Low
Table 2. ATtiny26(L) I/O Space
(1)
(Continued)
Address Hex Name Function
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