23
ATtiny26(L)
1477G–AVR–03/05
Internal PLL for Fast
Peripheral Clock Generation –
clk
PCK
The internal PLL in ATtiny26(L) generates a clock frequency that is 64x multiplied from
nominally 1 MHz input. The source of the 1 MHz PLL input clock is the output of the
internal RC Oscillator which is automatically divided down to 1 MHz, if needed. See the
Figure 21 on page 23. When the PLL reference frequency is the nominal 1 MHz, the fast
peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can
be selected as the clock source for Timer/Counter1.
The PLL is locked on the RC Oscillator and adjusting the RC Oscillator via OSCCAL
Register will adjust the fast peripheral clock at the same time. However, even if the pos-
sibly divided RC Oscillator is taken to a higher frequency than 1 MHz, the fast peripheral
clock frequency saturates at 70 MHz (worst case) and remains oscillating at the maxi-
mum frequency. It should be noted that the PLL in this case is not locked any more with
the RC Oscillator clock.
Therefore it is recommended not to take the OSCCAL adjustments to a higher fre-
quency than 1 MHz in order to keep the PLL in the correct operating range. The internal
PLL is enabled only when the PLLE bit in the register PLLCSR is set or the PLLCK Fuse
is programmed (“0”). The bit PLOCK from the register PLLCSR is set when PLL is
locked.
Both internal 1 MHz RC Oscillator and PLL are switched off in Power-down and Standby
sleep modes.
Figure 21. PCK Clocking System
1
2
4
8 MHz
RC OSCILLATOR
OSCCAL
XTAL1
XTAL2
OSCILLATORS
DIVIDE
TO 1 MHz
DIVIDE
BY 4
CK
PLL
64x
PLLCK &
CKSEL
FUSES
PLLE
PCK
Lock
Detector
PLOCK
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