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General| Brand | Atmel |
|---|---|
| Model | ATtiny26 |
| Category | Microcontrollers |
| Language | English |
High-performance, low-power 8-bit AVR microcontroller with RISC architecture.
Describes the RISC architecture of the ATtiny26(L) microcontroller.
Details the Flash, EEPROM, and SRAM memory specifications.
Lists peripheral features like Timers, ADC, Comparator.
Highlights features like low power modes, reset, interrupts.
Defines the operating voltage ranges for ATtiny26L and ATtiny26.
Specifies the operating speed ranges for ATtiny26L and ATtiny26.
Details power consumption in active and idle modes.
Describes Port A as an 8-bit general purpose I/O port with alternate functions.
Describes Port B as an 8-bit general purpose I/O port with alternate functions.
Explains the AVR RISC architecture and register file concept.
Details direct register addressing for two registers.
Explains direct addressing for I/O memory locations.
Describes indirect addressing with displacement calculation.
Explains indirect addressing with pre-decrement operation.
Details indirect addressing with post-increment operation.
Covers indirect addressing for program memory jumps and calls.
Details the 2K byte in-system programmable Flash memory for program storage.
Describes the 128 bytes of internal SRAM organization and usage.
Covers the 128 bytes of EEPROM memory, organization, and read/write access.
Lists selectable clock source options via Flash Fuse bits.
Details the on-chip detection circuit for power-on reset generation.
Explains how to generate an external reset via the RESET pin.
Describes the on-chip BOD circuit for monitoring VCC level during operation.
Contains control bits for general MCU functions, including sleep modes.
Stops CPU, allows peripherals to run; halts clkCPU and clkFLASH.
Halts clkIO, clkCPU, clkFLASH; improves ADC noise environment.
Stops external oscillator; halts most clocks, allows async modules to run.
Similar to power-down, but keeps the oscillator running.
Describes bi-directional I/O ports with optional internal pull-ups.
Details alternate functions for port pins beyond general digital I/O.
Lists interrupt sources, program vectors, and priority levels.
Explains interrupt occurrence, disabling, and response time.
Details the 8-bit Timer/Counter0, its block diagram, and control registers.
Covers Timer/Counter1 modes, prescalers, and PWM capabilities.
Describes USI data register, status register, and control register.
Explains three-wire and two-wire modes, and alternative USI usages.
Lists key features of the 10-bit successive approximation ADC.
Explains how to find and interpret the ADC conversion result.
Details lock bits for protecting Flash and EEPROM programming.
Describes the algorithm to put the device into parallel programming mode.
Explains programming via the serial SPI bus interface.
Lists the stress limits beyond which damage may occur to the device.
Provides DC electrical parameters like voltage thresholds and currents.
Details ADC performance metrics for single-ended and differential channels.
Details the 20-lead PDIP package dimensions and specifications.
Details the 20-lead SOIC package dimensions and specifications.
Details the 32-pad MLF package dimensions and specifications.
