DSB75 Development Support Board Rev. B1 Hardware Description
Confidential / Released
DSB75_hd_v12 Page 8 of 96 2008-08-26
Chapter What is new
• GPIO7 -> SPICS
• GPIO7_I -> SPICS_I
• GPIO7_SPI -> SPI1_CS
• GPIO8 -> SPIDI
• GPIO8_I -> SPIDI_I
• GPIO8_SPI -> SPI1_DI
Preceding document: "DSB75 Development Support Board Rev B1 Hardware Description", v07
New document: "
DSB75 Development Support Board Rev. B1 Hardware Description" Version v08
Chapter What is new
3.6.2 Added description of EPREF.
3.6.2.2,
3.6.3
Added information about required bias voltage for speakerphone operations.
3.7 Table 16: Updated pin description of PCM interface.
Preceding document: "DSB75 Development Support Board Rev B1 Hardware Description", v06
New document: "
DSB75 Development Support Board Rev. B1 Hardware Description" Version v07
Chapter What is new
7.1 Modified section “Toggling low-high state of DTR”.
8 Table 35: DSB75 technical data: Added Ignition key, Emergency key, Ignition via DTR,
Ignition via USB
Preceding document: "DSB75 Development Support Board Rev B1 Hardware Description", v05
New document: "
DSB75 Development Support Board Rev. B1 Hardware Description" Version v06
Chapter What is new
9.2 Figure 56: Schematic sheet 6 – charging interface – corrected value of R604
Preceding document: "DSB75 Development Support Board Rev B1 Hardware Description", v04
New document: "
DSB75 Development Support Board Rev. B1 Hardware Description" v05
Chapter What is new
2.2 Modified Figure 2: Location of the connectors, switches, jumpers, LEDs and adjustable
resistors
3.1 Corrected Table 5: Pin assignment of B2B connector X100 and Table 6: Pin
assignment – B2B connector X100 and test points X101
Board-to-board connector X100 will be supplied by Molex
3.3 Added note that the status of GPIOs 1 – 6 and 9 – 10 will be indicated by LEDs.
Deleted test pin X102 for connecting measurement equipment or an external
application. Corrected
Table 9: GPIO assignment and switch position
3.5.1 Table 11: Pin assignment of 1st serial interface COM1 (X201) – modified note on DTR line
3.11 Table 22: Alternative configuration of SPI interface lines – deleted GPIO as alternative