Denon LA-3500 - Control

-LA-3500
48
IC SM5841 AS (IC602)
22
II
Block Diagram
XTI
XTO
CKO
MDT
MCK
MLE
I
CKSL
TIMING
CONTROLLER
MODE AND
ATTENUATOR
INTERFACE
LRCI
MODE
CONTROL
DIN
BCKI
----.,
INPUT DATA
INTERFACE
FILTER C ALCULATION AND
ATTENUATION CALCULATION
BLOCK
OUTPUT
DATA
INTERFACE
I
1 ATTENUATOR - MUTE CONTROL
L _____ -- - --- - - --- - - - ~ -l--- -- - _ _j
Vss
voo
SM5841AS Terminal Function
Pin No.
Symbol 1/0
Funct io n
DIP SOP
--
Oscillation and input frequency selection. (3B4fs at CKSL = H)
1 1
CKSL
IP
{256fs at CKSL = L)
2 2
X TI I
Oscillation
section input terminal.
(Selects
frequency by CKSL)
3 3 XTO 0
Oscillation section output terminal.
4 4 CKO 0
Oscillation section output clock (Frequen cy is same as X TI terminal).
5 5
Vss
-
GND terminal.
-
6
NC
-
-
7 NC -
6 B
MDT
IP Mode set data.
7
9
MCK
IP Mode set clock.
Performs setting of digital attenuator and mode flag register.
--
B
10 MLE IP Mode set latch enable.
9
11 RST IP System reset (Initialize).
10 12 DG 0
Deglitch output: At Bis LR parallel output mode.
Deglitch output:
At 4fs LR alternate output mode .
11
13
DOR
0
Reh data output: At Bis LR parallel output mode.
LR clock output: At 4fs LR alternate output mode.
12 14 DOL
0
Leh data output: At Bfs LR parallel output mode.
LR data output: At 4fs LR alternate output mode.
13 15 WCKO 0 Output word clock.
14 16
VDD
- Power supply terminal (5V; standard).
- 17 NC
-
-
1B NC
-
15 19
BCKO
0
Output bit clock.
16 20
LACI
IP
Sample rate (Is) clock of input data.
17
21
BCKI
IP
Input bit clock.
1B 22 DIN
IP Input data.
I: lnputTerm1nal IP: Input Terminal with pullup resistor.
0: Output Terminal
BCKO
WCKO
DOL
DOR
DG