Furuno DSC-60 - Page 17

2-7
3. Function and overview of each board
Receiver block diagram Receiver block diagram Receiver block diagram Receiver block diagram
Receiver block diagram
1st Lo level (TP1) : more than 0.8Vp-p 2nd Lo level (TP3) : more than 70mVp-p 3rd Lo level (TP4) : more than 250mVp-p
+15V
+15V
54.455MHz
Q5
Q4
U1
CR4
E1
CR5
2SK937
CR6
SMS3927-023
FL1
54.455MHz
AN78L12
+15V
U5
AN7805F
ACTIVE
J3
Y08U90B
ANT
1Lo 2Lo 3Lo
TEST SIG
F+54.455MHz 456.7kHz54MHz
CW 18MHz
TEST
U3,4
+15V
RX SYN
2 AF OUT
1 INST 4 CLK 5 DATA 6 ST SYN 8 DDS CLK 9 DDS DATA 13 +15V 15/16 OVEN(+24V)
L/C FIL
Q2,3
MJ4558M
2SC2498
2SC1815-Y
2SK192A-GR
TP1 TP2
TP6
TP4
TP3
J2
J1
12 UNLOCK 11 DDS3 LOAD 10 DDS1 LOAD 7 PLL1 ENB
Ref.OSC (36MHz)
FL2
455kHz
DET
54MHz
456.7kHz
U2
BA4116FV
AFSK *1700Hz+85Hz *0dBm/600ohms
F1B(J2B) * 50ohms/0dB
V
* F+85Hz
CONTROL/MODEM
(05P0702)
(Co)
Q7
J6 J7 DISTRESS ROUTINE
LPF-2:13.5 - 27.5MHz LPF-1:1.6 - 13.5MHz
1.6MHz
13.5MHz 27.5MHz
HPF
LPF-1
LPF-2
LPF 1 LPF 2
LPF CONT