Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 - Rpga988 B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)

Processor Pin and Signal Information
110 Datasheet, Volume 1
Figure 8-3. rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant)
V VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
U VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
T VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
R VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
P VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
N VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
M
PEG_R
X#[1]
VSS
PEG_T
X[1]
PEG_T
X#[1]
PEG_T
X#[2]
PEG_T
X[2]
PEG_T
X#[0]
PEG_T
X[0]
VCCS
A
VCCS
A
L
PEG_R
X[1]
PEG_R
X#[2]
VSS
PEG_T
X#[3]
PEG_T
X[3]
VSS
PEG_T
X#[4]
PEG_T
X[4]
VSS
VCCS
A
K VSS
PEG_R
X[2]
PEG_R
X#[0]
VSS
PEG_T
X#[5]
PEG_T
X[5]
VSS
PEG_T
X#[6]
PEG_T
X[6]
VSS
J
PEG_R
X#[3]
VSS
PEG_R
X[0]
PEG_R
X#[4]
VSS
PEG_T
X#[7]
PEG_T
X[7]
PEG_T
X#[8]
PEG_T
X[8]
VCCS
A
VCCS
A
VCCS
A
VCCI
O
PEG_I
COMPI
PEG_I
COMP
O
RSVD
FDI0_
LSYNC
FDI0_
FSYNC
H
PEG_R
X[3]
PEG_R
X#[5]
VSS
PEG_R
X[4]
PEG_R
X#[6]
VSS
PEG_T
X#[9]
PEG_T
X[9]
VSS
VCCS
A
VCCS
A
VSS
VCCS
A_SEN
SE
PEG_R
COMP
O
VSS
FDI_I
NT
FDI0_
TX#[1
]
VSS
G VSS
PEG_R
X[5]
PEG_R
X#[7]
VSS
PEG_R
X[6]
PEG_R
X#[8]
VSS
PEG_T
X[10]
PEG_T
X#[10
]
VSS RSVD RSVD VSS
DMI_T
X[0]
DMI_T
X#[0]
VSS
FDI0_
TX[1]
FDI0_
TX[3]
F
PEG_R
X#[9]
VSS
PEG_R
X[7]
PEG_R
X[11]
VSS
PEG_R
X[8]
VSS
PEG_T
X[12]
PEG_T
X#[12
]
PEG_T
X#[14
]
RSVD RSVD RSVD VSS
DMI_T
X#[2]
DMI_T
X[2]
VSS
FDI0_
TX#[3
]
E
PEG_R
X[9]
PEG_R
X#[10
]
PEG_R
X[10]
PEG_R
X#[11
]
PEG_R
X[13]
VSS
PEG_T
X#[11
]
PEG_T
X[11]
VSS
PEG_T
X[14]
PEG_T
X#[15
]
VSS RSVD
DMI_T
X#[1]
VSS
FDI0_
TX[2]
FDI0_
TX#[2
]
VSS
D VSS
PEG_R
X[12]
PEG_R
X#[12
]
VSS
PEG_R
X#[13
]
RSVD VSS
PEG_T
X#[13
]
PEG_T
X[13]
VSS
PEG_T
X[15]
RSVD RSVD
DMI_T
X[1]
DMI_T
X#[3]
VSS
FDI1_
TX[2]
FDI1_
TX#[2
]
C
RSVD
_NCTF
VSS
PEG_R
X[14]
PEG_R
X#[15
]
VSS RSVD RSVD VSS VSS
PROC
_SELE
CT#
VSS
VCCS
A_VID
[
1
]
VSS
VCCS
A_VID
[
0
]
DMI_T
X[3]
FDI1_
TX#[1
]
FDI1_
TX[1]
eDP_T
X#[0]
B
RSVD
_NCTF
RSVD
_NCTF
PEG_R
X#[14
]
PEG_R
X[15]
RSVD RSVD RSVD
DMI_R
X[0]
DMI_R
X#[0]
DMI_R
X[1]
DMI_R
X#[1]
DMI_R
X#[3]
DMI_R
X[3]
VSS
FDI1_
TX#[0
]
FDI1_
TX[0]
VSS RSVD
A VSS
RSVD
_NCTF
RSVD
_NCTF
VSS RSVD RSVD VSS BCLK
BCLK
#
VSS
DMI_R
X#[2]
DMI_R
X[2]
VSS
FDI0_
TX[0]
FDI0_
TX#[0
]
VSS
VCCI
O_SEL
eDP_C
OMPIO
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