Datasheet, Volume 1 15
Introduction
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
— DMI -> PCI Express* Port 1
— PCI Express* Port 0 -> DMI
— PCI Express* Port 1 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Static lane numbering reversal
— Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification.
• Supports Half Swing “low-power/low-voltage” mode.
Note: The processor does not support PCI Express* Hot-Plug.
1.2.3 Direct Media Interface (DMI)
• DMI 2.0 support
• Four lanes in each direction
• 5 GT/s point-to-point DMI interface to PCH is supported
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
• Shares 100-MHz PCI Express* reference clock
Intel
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