Intel 2ND GENERATION INTEL CORE PROCESSOR FAMILY MOBILE - DATASHEET VOLUME 1 01-2011 - Idle Power Management Breakdown of the Processor Cores; Thread and Core C-State Entry and Exit

Datasheet, Volume 1 49
Power Management
Entry and exit of the C-States at the thread and core level are shown in Figure 4-2.
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Figure 4-1. Idle Power Management Breakdown of the Processor Cores
Processor Package State
Core 1 State
Thread 1Thread 0
Core 0 State
Thread 1Thread 0
Figure 4-2. Thread and Core C-State Entry and Exit
C1 C1 E C7C6C3
C0
MWAIT(C1), HLT
C0
MWAIT(C7),
P_LVL4 I/O Read
MWAIT(C6),
P_LVL3 I/O Read
MWAIT(C3),
P_LVL2 I/O Read
MWAIT(C1), HLT
(C1E Enabled)