Electrical Specifications
92 Datasheet, Volume 1
7.4 System Agent (SA) V
CC
VID
The Vcc
SA
is configured by the processor output pins VCCSA_VID[1:0].
VCCSA_VID[0] output default logic state is low for the 2nd Generation Intel
®
Core™
processor family mobile; logic high is reserved for future compatibility.
VCCSA_VID[1] output default logic state is low – will not change the SA voltage. Logic
high will reduce the voltage.
Note: During boot, the processor’s Vcc
SA
is 0.9 V.
Table 7-2 specifies the different VCCSA_VID configurations.
Notes:
1. Some of V
CCSA
configurations are reserved for future Intel processor families.
7.5 Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD – these signals should not be connected
• RSVD_TP – these signals should be routed to a test point
• RSVD_NCTF – these signals are non-critical to function and may be left un-
connected
Arbitrary connection of these signals to V
CC
, V
CCIO
, V
DDQ
, V
CCPLL
, V
CCSA,
V
AXG
, V
SS
, or
to any other signal (including each other) may result in component malfunction or
incompatibility with future processors. See Chapter 8 for a pin listing of the processor
and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (V
SS
). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability.
Table 7-2. VCCSA_VID configuration
Processor family VCCSA_VID[0] VCCSA_VID[1]
Selected VCCSA
(XE and SV
segments)
Selected VCCSA
(LV and ULV
segments)
2nd Generation Intel
®
Core™ processor Family
Mobile
0 0 0.9 V 0.9 V
0 1 0.8 V 0.85 V
Future Intel processors 1 0 Note 1 Note 1
11Note 1Note 1
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